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Merge pull request #10844 from SparkiDev/windows_arm64_1

Browse Source 
ARM64 Windows: Add assembly
This commit is contained in:
David Garske
2026-07-08 09:28:41 -07:00
committed by GitHub
parent 0d02f2fe2f 2bcb4efb5b
commit 59e942b07a
26 changed files with 84164 additions and 40 deletions
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57
.github/workflows/windows-arm64.yml vendored Normal file
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@@ -0,0 +1,57 @@
name: Windows ARM64 Test
# Builds and tests wolfSSL on a native Windows-on-ARM64 runner. Unlike the
# cross-compiled ARM64 job in os-check.yml (which runs on an x64 runner and can
# only build), this runs on GitHub's native windows-11-arm image so the test
# suite executes on the target ISA. The WolfSSLAarch64Asm=true leg assembles
# the ARMv8 crypto .asm (armasm64) and enables the WOLFSSL_ARMASM code paths.
on:
push:
branches: [ 'release/**' ]
paths-ignore:
- '**/*.md'
- 'doc/**'
pull_request:
types: [opened, synchronize, reopened, ready_for_review]
branches: [ '*' ]
paths-ignore:
- '**/*.md'
- 'doc/**'
concurrency:
group: ${{ github.workflow }}-${{ github.ref }}
cancel-in-progress: true
jobs:
windows_arm64_build:
name: Windows ARM64 Build Test
if: ${{ (github.repository_owner == 'wolfssl') && (github.event_name != 'pull_request' || github.event.pull_request.draft == false) }}
runs-on: windows-11-arm
strategy:
fail-fast: false
matrix:
# false: pure-C ARM64 build. true: assemble the ARMv8 crypto .asm and
# enable the matching WOLFSSL_ARMASM code paths.
asm: [ false, true ]
timeout-minutes: 10
env:
SOLUTION_FILE_PATH: wolfssl64.sln
BUILD_CONFIGURATION: Release
steps:
- uses: actions/checkout@v5
- name: Add MSBuild to PATH
uses: microsoft/setup-msbuild@v3
- name: Restore NuGet packages
working-directory: ${{env.GITHUB_WORKSPACE}}
run: nuget restore ${{env.SOLUTION_FILE_PATH}}
- name: Build
working-directory: ${{env.GITHUB_WORKSPACE}}
run: msbuild /m /p:PlatformToolset=v143 /p:Platform=ARM64 /p:Configuration=${{env.BUILD_CONFIGURATION}} /p:WolfSSLAarch64Asm=${{matrix.asm}} ${{env.SOLUTION_FILE_PATH}}
- name: Run Test
working-directory: ${{env.GITHUB_WORKSPACE}}
run: Release/ARM64/testsuite.exe

7
examples/client/client.vcxproj
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@@ -486,6 +486,13 @@
<PreprocessorDefinitions>USE_INTEL_SPEEDUP;WOLFSSL_X86_64_BUILD;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<!-- Keep WOLFSSL_ARMASM consistent with the library (set by
/p:WolfSSLAarch64Asm=true) so struct layouts match. -->
<ItemDefinitionGroup Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">
<ClCompile>
<PreprocessorDefinitions>WOLFSSL_ARMASM;WOLFSSL_ARMASM_CRYPTO_SHA3;WOLFSSL_ARMASM_CRYPTO_SHA512;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

7
examples/echoclient/echoclient.vcxproj
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@@ -486,6 +486,13 @@
<PreprocessorDefinitions>USE_INTEL_SPEEDUP;WOLFSSL_X86_64_BUILD;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<!-- Keep WOLFSSL_ARMASM consistent with the library (set by
/p:WolfSSLAarch64Asm=true) so struct layouts match. -->
<ItemDefinitionGroup Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">
<ClCompile>
<PreprocessorDefinitions>WOLFSSL_ARMASM;WOLFSSL_ARMASM_CRYPTO_SHA3;WOLFSSL_ARMASM_CRYPTO_SHA512;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

7
examples/echoserver/echoserver.vcxproj
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@@ -486,6 +486,13 @@
<PreprocessorDefinitions>USE_INTEL_SPEEDUP;WOLFSSL_X86_64_BUILD;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<!-- Keep WOLFSSL_ARMASM consistent with the library (set by
/p:WolfSSLAarch64Asm=true) so struct layouts match. -->
<ItemDefinitionGroup Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">
<ClCompile>
<PreprocessorDefinitions>WOLFSSL_ARMASM;WOLFSSL_ARMASM_CRYPTO_SHA3;WOLFSSL_ARMASM_CRYPTO_SHA512;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

7
examples/server/server.vcxproj
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@@ -486,6 +486,13 @@
<PreprocessorDefinitions>USE_INTEL_SPEEDUP;WOLFSSL_X86_64_BUILD;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<!-- Keep WOLFSSL_ARMASM consistent with the library (set by
/p:WolfSSLAarch64Asm=true) so struct layouts match. -->
<ItemDefinitionGroup Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">
<ClCompile>
<PreprocessorDefinitions>WOLFSSL_ARMASM;WOLFSSL_ARMASM_CRYPTO_SHA3;WOLFSSL_ARMASM_CRYPTO_SHA512;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

7
sslSniffer/sslSniffer.vcxproj
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@@ -264,6 +264,13 @@
<PreprocessorDefinitions>USE_INTEL_SPEEDUP;WOLFSSL_X86_64_BUILD;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<!-- Keep WOLFSSL_ARMASM consistent with the library (set by
/p:WolfSSLAarch64Asm=true) so struct layouts match. -->
<ItemDefinitionGroup Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">
<ClCompile>
<PreprocessorDefinitions>WOLFSSL_ARMASM;WOLFSSL_ARMASM_CRYPTO_SHA3;WOLFSSL_ARMASM_CRYPTO_SHA512;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

7
sslSniffer/sslSnifferTest/sslSniffTest.vcxproj
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@@ -265,6 +265,13 @@
<PreprocessorDefinitions>USE_INTEL_SPEEDUP;WOLFSSL_X86_64_BUILD;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<!-- Keep WOLFSSL_ARMASM consistent with the library (set by
/p:WolfSSLAarch64Asm=true) so struct layouts match. -->
<ItemDefinitionGroup Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">
<ClCompile>
<PreprocessorDefinitions>WOLFSSL_ARMASM;WOLFSSL_ARMASM_CRYPTO_SHA3;WOLFSSL_ARMASM_CRYPTO_SHA512;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

7
testsuite/testsuite.vcxproj
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@@ -492,6 +492,13 @@
<PreprocessorDefinitions>USE_INTEL_SPEEDUP;WOLFSSL_X86_64_BUILD;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<!-- Keep WOLFSSL_ARMASM consistent with the library (set by
/p:WolfSSLAarch64Asm=true) so struct layouts match. -->
<ItemDefinitionGroup Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">
<ClCompile>
<PreprocessorDefinitions>WOLFSSL_ARMASM;WOLFSSL_ARMASM_CRYPTO_SHA3;WOLFSSL_ARMASM_CRYPTO_SHA512;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

67
wolfcrypt/src/cpuid.c
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@@ -411,6 +411,73 @@
new_cpuid_flags |= CPUID_SM4;
#endif
(void)wolfSSL_Atomic_Uint_CompareExchange
(&cpuid_flags, &old_cpuid_flags, new_cpuid_flags);
}
}
#elif defined(_WIN32)
/* Windows on ARM64. IsProcessorFeaturePresent() is the documented way to
* query instruction-set extensions: NEON (the 32x64-bit VFP register bank),
* the mandatory ARMv8 crypto extension (AES / PMULL / SHA-1 / SHA-256,
* reported as one feature), and the optional FEAT_SHA3 / FEAT_SHA512
* extensions each have their own flag. FEAT_RDM (SQRDMLSH, ARMv8.1) has no
* dedicated flag, so it is gated on the ARMv8.2 dot-product feature. */
#include <windows.h>
/* Older Windows SDKs may not define these processor-feature constants. */
#ifndef PF_ARM_VFP_32_REGISTERS_AVAILABLE
#define PF_ARM_VFP_32_REGISTERS_AVAILABLE 18
#endif
#ifndef PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE
#define PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE 30
#endif
#ifndef PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE
#define PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE 64
#endif
#ifndef PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE
#define PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE 65
#endif
/* No dedicated flag for FEAT_RDM (ARMv8.1); gate on ARMv8.2 dot-product -
* a CPU reporting v8.2 DP necessarily implements the v8.1 RDM (SQRDMLSH)
* instructions the ML-KEM assembly uses. */
#ifndef PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE
#define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE 43
#endif
static WC_INLINE void cpuid_set_flags(void)
{
if (WOLFSSL_ATOMIC_LOAD(cpuid_flags) == WC_CPUID_INITIALIZER) {
cpuid_flags_t new_cpuid_flags = 0,
old_cpuid_flags = WC_CPUID_INITIALIZER;
#ifndef WOLFSSL_ARMASM_NO_NEON
if (IsProcessorFeaturePresent(PF_ARM_VFP_32_REGISTERS_AVAILABLE))
new_cpuid_flags |= CPUID_ASIMD;
#endif
#ifndef WOLFSSL_ARMASM_NO_HW_CRYPTO
if (IsProcessorFeaturePresent(
PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) {
new_cpuid_flags |= CPUID_AES;
new_cpuid_flags |= CPUID_PMULL;
new_cpuid_flags |= CPUID_SHA256;
}
#endif
#ifdef WOLFSSL_ARMASM_CRYPTO_SHA512
if (IsProcessorFeaturePresent(
PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE))
new_cpuid_flags |= CPUID_SHA512;
#endif
#if !defined(WOLFSSL_AARCH64_NO_SQRDMLSH)
if (IsProcessorFeaturePresent(
PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE))
new_cpuid_flags |= CPUID_RDM;
#endif
#ifdef WOLFSSL_ARMASM_CRYPTO_SHA3
if (IsProcessorFeaturePresent(
PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE))
new_cpuid_flags |= CPUID_SHA3;
#endif
(void)wolfSSL_Atomic_Uint_CompareExchange
(&cpuid_flags, &old_cpuid_flags, new_cpuid_flags);
}

18
wolfcrypt/src/fe_x25519_asm.asm
View File

@@ -4631,6 +4631,15 @@ L_curve25519_x64_bits:
adc r11, r14
adc r12, r15
adc r13, rdi
mov rbp, 9223372036854775807
mov rax, r13
sar rax, 63
and rax, 19
and r13, rbp
add rcx, rax
adc r11, 0
adc r12, 0
adc r13, 0
; Store
mov QWORD PTR [rsp+64], rcx
mov QWORD PTR [rsp+72], r11
@@ -14299,6 +14308,15 @@ L_curve25519_avx2_bits:
adcx r13, rbx
adox r14, rsi
adcx r14, rcx
mov rcx, 9223372036854775807
mov rdx, r14
sar rdx, 63
and rdx, 19
and r14, rcx
add r11, rdx
adc r12, 0
adc r13, 0
adc r14, 0
; Store
mov QWORD PTR [rsp+64], r11
mov QWORD PTR [rsp+72], r12

8
wolfcrypt/src/include.am
View File

@@ -29,6 +29,14 @@ EXTRA_DIST += wolfcrypt/src/sha512_asm.asm
EXTRA_DIST += wolfcrypt/src/sha3_asm.asm
EXTRA_DIST += wolfcrypt/src/wc_mlkem_asm.asm
EXTRA_DIST += wolfcrypt/src/wc_mldsa_asm.asm
EXTRA_DIST += wolfcrypt/src/port/arm/armv8-aes-asm.asm
EXTRA_DIST += wolfcrypt/src/port/arm/armv8-chacha-asm.asm
EXTRA_DIST += wolfcrypt/src/port/arm/armv8-curve25519.asm
EXTRA_DIST += wolfcrypt/src/port/arm/armv8-mlkem-asm.asm
EXTRA_DIST += wolfcrypt/src/port/arm/armv8-poly1305-asm.asm
EXTRA_DIST += wolfcrypt/src/port/arm/armv8-sha256-asm.asm
EXTRA_DIST += wolfcrypt/src/port/arm/armv8-sha3-asm.asm
EXTRA_DIST += wolfcrypt/src/port/arm/armv8-sha512-asm.asm
EXTRA_DIST += wolfcrypt/src/wc_dsp.c
EXTRA_DIST += wolfcrypt/src/sp_dsp32.c
EXTRA_DIST += wolfcrypt/src/sp_x86_64_asm.asm

40
wolfcrypt/src/port/arm/armv8-aes-asm.S
View File

@@ -44193,9 +44193,7 @@ L_AES_GCMSIV_ctr_aarch64_done:
#endif /* WOLFSSL_AESGCM_SIV */
#endif /* !WOLFSSL_ARMASM_NO_HW_CRYPTO */
#ifndef WOLFSSL_ARMASM_NO_NEON
#if defined(HAVE_AES_DECRYPT) || defined(HAVE_AES_CBC) || \
defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
#if defined(HAVE_AES_DECRYPT) || defined(HAVE_AES_CBC) || defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
#ifndef __APPLE__
.text
.section .rodata
@@ -44260,8 +44258,7 @@ L_AES_ARM64_NEON_te:
L_AES_ARM64_NEON_shift_rows_shuffle:
.byte 0x0c,0x09,0x06,0x03,0x00,0x0d,0x0a,0x07
.byte 0x04,0x01,0x0e,0x0b,0x08,0x05,0x02,0x0f
#endif /* HAVE_AES_DECRYPT || HAVE_AES_CBC || HAVE_AESCCM || HAVE_AESGCM ||
* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER */
#endif /* HAVE_AES_DECRYPT || HAVE_AES_CBC || HAVE_AESCCM || HAVE_AESGCM || WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER */
#ifdef HAVE_AES_DECRYPT
#ifndef __APPLE__
.text
@@ -44588,9 +44585,7 @@ L_AES_set_encrypt_key_NEON_end:
#ifndef __APPLE__
.size AES_set_encrypt_key_NEON,.-AES_set_encrypt_key_NEON
#endif /* __APPLE__ */
#if defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_ECB)
#if defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || defined(HAVE_AES_ECB)
#ifndef __APPLE__
.text
.globl AES_ECB_encrypt_NEON
@@ -45369,8 +45364,7 @@ L_AES_ECB_encrypt_NEON_data_done:
#ifndef __APPLE__
.size AES_ECB_encrypt_NEON,.-AES_ECB_encrypt_NEON
#endif /* __APPLE__ */
#endif /* HAVE_AESCCM || HAVE_AESGCM || WOLFSSL_AES_DIRECT ||
* WOLFSSL_AES_COUNTER || HAVE_AES_ECB */
#endif /* HAVE_AESCCM || HAVE_AESGCM || WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_ECB */
#ifdef HAVE_AES_CBC
#ifndef __APPLE__
.text
@@ -46365,8 +46359,7 @@ L_AES_CTR_encrypt_NEON_data_done:
#endif /* __APPLE__ */
#endif /* WOLFSSL_AES_COUNTER */
#ifdef HAVE_AES_DECRYPT
#if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_CBC) || defined(HAVE_AES_ECB)
#if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || defined(HAVE_AES_CBC) || defined(HAVE_AES_ECB)
#ifndef __APPLE__
.text
.section .rodata
@@ -48552,8 +48545,7 @@ L_AES_CBC_decrypt_NEON_data_done:
.size AES_CBC_decrypt_NEON,.-AES_CBC_decrypt_NEON
#endif /* __APPLE__ */
#endif /* HAVE_AES_CBC */
#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_CBC
* HAVE_AES_ECB */
#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_CBC || HAVE_AES_ECB */
#endif /* HAVE_AES_DECRYPT */
#ifdef HAVE_AESGCM
#ifndef __APPLE__
@@ -53650,9 +53642,7 @@ L_AES_ARM64_td:
.long 0x7139a801,0xde080cb3,0x9cd8b4e4,0x906456c1
.long 0x617bcb84,0x70d532b6,0x74486c5c,0x42d0b857
#endif /* HAVE_AES_DECRYPT */
#if defined(HAVE_AES_DECRYPT) || defined(HAVE_AES_CBC) || \
defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
#if defined(HAVE_AES_DECRYPT) || defined(HAVE_AES_CBC) || defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
#ifndef __APPLE__
.text
.section .rodata
@@ -53732,8 +53722,7 @@ L_AES_ARM64_te:
.long 0xda65bfbf,0x31d7e6e6,0xc6844242,0xb8d06868
.long 0xc3824141,0xb0299999,0x775a2d2d,0x111e0f0f
.long 0xcb7bb0b0,0xfca85454,0xd66dbbbb,0x3a2c1616
#endif /* HAVE_AES_DECRYPT || HAVE_AES_CBC || HAVE_AESCCM || HAVE_AESGCM ||
* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER */
#endif /* HAVE_AES_DECRYPT || HAVE_AES_CBC || HAVE_AESCCM || HAVE_AESGCM || WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER */
#ifdef HAVE_AES_DECRYPT
#ifndef __APPLE__
.text
@@ -54142,9 +54131,7 @@ L_AES_set_encrypt_key_end:
#ifndef __APPLE__
.size AES_set_encrypt_key,.-AES_set_encrypt_key
#endif /* __APPLE__ */
#if defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_ECB)
#if defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || defined(HAVE_AES_ECB)
#ifndef __APPLE__
.text
.globl AES_ECB_encrypt
@@ -54475,8 +54462,7 @@ L_AES_ECB_encrypt_loop_nr:
#ifndef __APPLE__
.size AES_ECB_encrypt,.-AES_ECB_encrypt
#endif /* __APPLE__ */
#endif /* HAVE_AESCCM || HAVE_AESGCM || WOLFSSL_AES_DIRECT ||
* WOLFSSL_AES_COUNTER || HAVE_AES_ECB */
#endif /* HAVE_AESCCM || HAVE_AESGCM || WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_ECB */
#ifdef HAVE_AES_CBC
#ifndef __APPLE__
.text
@@ -55160,8 +55146,7 @@ L_AES_CTR_encrypt_loop_nr:
#endif /* __APPLE__ */
#endif /* WOLFSSL_AES_COUNTER */
#ifdef HAVE_AES_DECRYPT
#if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_CBC) || defined(HAVE_AES_ECB)
#if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || defined(HAVE_AES_CBC) || defined(HAVE_AES_ECB)
#ifndef __APPLE__
.text
.section .rodata
@@ -56119,8 +56104,7 @@ L_AES_CBC_decrypt_end_dec:
.size AES_CBC_decrypt,.-AES_CBC_decrypt
#endif /* __APPLE__ */
#endif /* HAVE_AES_CBC */
#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_CBC
* HAVE_AES_ECB */
#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_CBC || HAVE_AES_ECB */
#endif /* HAVE_AES_DECRYPT */
#ifdef HAVE_AESGCM
#ifndef __APPLE__

55923
wolfcrypt/src/port/arm/armv8-aes-asm.asm Normal file
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File diff suppressed because it is too large Load Diff

24
wolfcrypt/src/port/arm/armv8-aes-asm_c.c
View File

@@ -44574,8 +44574,8 @@ void AES_GCMSIV_ctr_aarch64(const unsigned char* in, unsigned char* out,
#endif /* !WOLFSSL_ARMASM_NO_HW_CRYPTO */
#ifndef WOLFSSL_ARMASM_NO_NEON
#if defined(HAVE_AES_DECRYPT) || defined(HAVE_AES_CBC) || \
defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
XALIGNED(4) static const word8 L_AES_ARM64_NEON_te[] = {
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
@@ -44911,8 +44911,8 @@ void AES_set_encrypt_key_NEON(const unsigned char* key, word32 len,
}
#if defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_ECB)
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_ECB)
void AES_ECB_encrypt_NEON(const unsigned char* in, unsigned char* out,
unsigned long len, const unsigned char* ks, int nr);
void AES_ECB_encrypt_NEON(const unsigned char* in, unsigned char* out,
@@ -46634,7 +46634,7 @@ void AES_CTR_encrypt_NEON(const unsigned char* in, unsigned char* out,
#endif /* WOLFSSL_AES_COUNTER */
#ifdef HAVE_AES_DECRYPT
#if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_CBC) || defined(HAVE_AES_ECB)
defined(HAVE_AES_CBC) || defined(HAVE_AES_ECB)
XALIGNED(4) static const word8 L_AES_ARM64_NEON_td[] = {
0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38,
0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
@@ -48770,7 +48770,7 @@ void AES_CBC_decrypt_NEON(const unsigned char* in, unsigned char* out,
}
#endif /* HAVE_AES_CBC */
#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_CBC
#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_CBC ||
* HAVE_AES_ECB */
#endif /* HAVE_AES_DECRYPT */
#ifdef HAVE_AESGCM
@@ -53726,8 +53726,8 @@ XALIGNED(8) static const word32 L_AES_ARM64_td[] = {
#endif /* HAVE_AES_DECRYPT */
#if defined(HAVE_AES_DECRYPT) || defined(HAVE_AES_CBC) || \
defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
XALIGNED(8) static const word32 L_AES_ARM64_te[] = {
0xa5c66363, 0x84f87c7c, 0x99ee7777, 0x8df67b7b,
0x0dfff2f2, 0xbdd66b6b, 0xb1de6f6f, 0x5491c5c5,
@@ -54169,8 +54169,8 @@ void AES_set_encrypt_key(const unsigned char* key, word32 len,
}
#if defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || \
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_ECB)
defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_ECB)
void AES_ECB_encrypt(const unsigned char* in, unsigned char* out,
unsigned long len, const unsigned char* ks, int nr);
void AES_ECB_encrypt(const unsigned char* in, unsigned char* out,
@@ -55149,7 +55149,7 @@ void AES_CTR_encrypt(const unsigned char* in, unsigned char* out,
#endif /* WOLFSSL_AES_COUNTER */
#ifdef HAVE_AES_DECRYPT
#if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || \
defined(HAVE_AES_CBC) || defined(HAVE_AES_ECB)
defined(HAVE_AES_CBC) || defined(HAVE_AES_ECB)
XALIGNED(4) static const word8 L_AES_ARM64_td4[] = {
0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38,
0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
@@ -56061,7 +56061,7 @@ void AES_CBC_decrypt(const unsigned char* in, unsigned char* out,
}
#endif /* HAVE_AES_CBC */
#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_CBC
#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_CBC ||
* HAVE_AES_ECB */
#endif /* HAVE_AES_DECRYPT */
#ifdef HAVE_AESGCM

1016
wolfcrypt/src/port/arm/armv8-chacha-asm.asm Normal file
View File

File diff suppressed because it is too large Load Diff

11490
wolfcrypt/src/port/arm/armv8-curve25519.asm Normal file
View File

File diff suppressed because it is too large Load Diff

11426
wolfcrypt/src/port/arm/armv8-mlkem-asm.asm Normal file
View File

File diff suppressed because it is too large Load Diff

645
wolfcrypt/src/port/arm/armv8-poly1305-asm.asm Normal file
View File

@@ -0,0 +1,645 @@
; /* armv8-poly1305-asm
; *
; * Copyright (C) 2006-2026 wolfSSL Inc.
; *
; * This file is part of wolfSSL.
; *
; * wolfSSL is free software; you can redistribute it and/or modify
; * it under the terms of the GNU General Public License as published by
; * the Free Software Foundation; either version 3 of the License, or
; * (at your option) any later version.
; *
; * wolfSSL is distributed in the hope that it will be useful,
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; * GNU General Public License for more details.
; *
; * You should have received a copy of the GNU General Public License
; * along with this program; if not, write to the Free Software
; * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
; */
; Generated using (from wolfssl):
; cd ../scripts
; ruby ./poly1305/poly1305.rb arm64 \
; ../wolfssl/wolfcrypt/src/port/arm/armv8-poly1305-asm.asm
AREA |.text|, CODE, READONLY
ALIGN 4
EXPORT poly1305_arm64_block_16
poly1305_arm64_block_16 PROC
; Load h
ldp w2, w3, [x0, #96]
ldp w4, w11, [x0, #104]
ldr w12, [x0, #112]
; Load m
ldr x14, [x1]
ldr x15, [x1, #8]
; Load r
ldp x5, x6, [x0]
; h: Base26 -> Base 64
add x2, x2, x3, lsl 26
lsr x3, x4, #12
add x2, x2, x4, lsl 52
add x3, x3, x11, lsl 14
lsr x4, x12, #24
add x3, x3, x12, lsl 40
; Add m and !finished at bit 128
adds x2, x2, x14
adcs x3, x3, x15
adc x4, x4, xzr
; Multiply h by r
; b[0] * a[0]
mul x7, x5, x2
umulh x8, x5, x2
; b[0] * a[1]
mul x10, x5, x3
umulh x9, x5, x3
; b[1] * a[0]
mul x11, x6, x2
umulh x12, x6, x2
adds x8, x8, x10
; b[1] * a[1]
mul x13, x6, x3
umulh x10, x6, x3
adc x9, x9, x12
adds x8, x8, x11
; b[0] * a[2]
mul x11, x5, x4
adcs x9, x9, x13
; b[1] * a[2]
mul x12, x6, x4
adc x10, x10, xzr
adds x9, x9, x11
adc x10, x10, x12
; Reduce mod 2^130 - 5
; Get high bits
and x11, x9, #-4
; Get top two bits
and x9, x9, #3
; Add top bits * 4
adds x2, x7, x11
; Move down 2 bits
extr x11, x10, x11, #2
adcs x3, x8, x10
lsr x10, x10, #2
adc x4, x9, xzr
; Add top bits.
adds x2, x2, x11
adcs x3, x3, x10
adc x4, x4, xzr
extr x12, x4, x3, #40
ubfx x4, x2, #52, #12
ubfx x11, x3, #14, #26
bfi x4, x3, #12, #14
ubfx x3, x2, #26, #26
ubfx x2, x2, #0, #26
stp w2, w3, [x0, #96]
stp w4, w11, [x0, #104]
str w12, [x0, #112]
ret
ENDP
AREA |.text|, CODE, READONLY
ALIGN 4
EXPORT poly1305_arm64_blocks
poly1305_arm64_blocks PROC
stp x29, x30, [sp, #-96]!
add x29, sp, #0
str x17, [x29, #24]
stp D8, D9, [x29, #32]
stp D10, D11, [x29, #48]
stp D12, D13, [x29, #64]
stp D14, D15, [x29, #80]
cmp x2, #0x40
blt L_poly1305_arm64_blocks_done
; Set mask (0x3ffffff), hi bit and 5 into vector registers
movi V25.16B, #0xff
movi V27.4S, #1, lsl 24
ushr V25.4S, V25.4S, #6
movi V24.4S, #5
ushll V26.2D, V25.2S, #0
add x14, x0, #16
ld4 {V15.4S, V16.4S, V17.4S, V18.4S}, [x14], #0x40
ld1 {V19.4S}, [x14]
add x14, x0, #0x60
movi V0.4S, #0
movi V1.4S, #0
movi V2.4S, #0
movi V3.4S, #0
movi V4.4S, #0
ld4 {V0.S, V1.S, V2.S, V3.S}[0], [x14], #16
ld1 {V4.S}[0], [x14]
mul V20.4S, V16.4S, V24.4S
mul V21.4S, V17.4S, V24.4S
mul V22.4S, V18.4S, V24.4S
mul V23.4S, V19.4S, V24.4S
L_poly1305_arm64_blocks_loop_64
; Load message of 64 bytes - setting hi bit for not finished
ld4 {V5.4S, V6.4S, V7.4S, V8.4S}, [x1], #0x40
sub x2, x2, #0x40
ushr V9.4S, V8.4S, #8
shl V8.4S, V8.4S, #18
orr V9.16B, V9.16B, V27.16B
sri V8.4S, V7.4S, #14
shl V7.4S, V7.4S, #12
and V8.16B, V8.16B, V25.16B
sri V7.4S, V6.4S, #20
shl V6.4S, V6.4S, #6
and V7.16B, V7.16B, V25.16B
sri V6.4S, V5.4S, #26
and V5.16B, V5.16B, V25.16B
and V6.16B, V6.16B, V25.16B
umull2 V10.2D, V5.4S, V15.4S
umull2 V11.2D, V5.4S, V16.4S
umull2 V12.2D, V5.4S, V17.4S
umull2 V13.2D, V5.4S, V18.4S
umull2 V14.2D, V5.4S, V19.4S
umlal2 V10.2D, V6.4S, V23.4S
umlal2 V11.2D, V6.4S, V15.4S
umlal2 V12.2D, V6.4S, V16.4S
umlal2 V13.2D, V6.4S, V17.4S
umlal2 V14.2D, V6.4S, V18.4S
umlal2 V10.2D, V7.4S, V22.4S
umlal2 V11.2D, V7.4S, V23.4S
umlal2 V12.2D, V7.4S, V15.4S
umlal2 V13.2D, V7.4S, V16.4S
umlal2 V14.2D, V7.4S, V17.4S
umlal2 V10.2D, V8.4S, V21.4S
umlal2 V11.2D, V8.4S, V22.4S
umlal2 V12.2D, V8.4S, V23.4S
umlal2 V13.2D, V8.4S, V15.4S
umlal2 V14.2D, V8.4S, V16.4S
umlal2 V10.2D, V9.4S, V20.4S
umlal2 V11.2D, V9.4S, V21.4S
umlal2 V12.2D, V9.4S, V22.4S
umlal2 V13.2D, V9.4S, V23.4S
umlal2 V14.2D, V9.4S, V15.4S
add V5.4S, V5.4S, V0.4S
add V6.4S, V6.4S, V1.4S
add V7.4S, V7.4S, V2.4S
add V8.4S, V8.4S, V3.4S
add V9.4S, V9.4S, V4.4S
umlal V10.2D, V5.2S, V15.2S
umlal V11.2D, V5.2S, V16.2S
umlal V12.2D, V5.2S, V17.2S
umlal V13.2D, V5.2S, V18.2S
umlal V14.2D, V5.2S, V19.2S
umlal V10.2D, V6.2S, V23.2S
umlal V11.2D, V6.2S, V15.2S
umlal V12.2D, V6.2S, V16.2S
umlal V13.2D, V6.2S, V17.2S
umlal V14.2D, V6.2S, V18.2S
umlal V10.2D, V7.2S, V22.2S
umlal V11.2D, V7.2S, V23.2S
umlal V12.2D, V7.2S, V15.2S
umlal V13.2D, V7.2S, V16.2S
umlal V14.2D, V7.2S, V17.2S
umlal V10.2D, V8.2S, V21.2S
umlal V11.2D, V8.2S, V22.2S
umlal V12.2D, V8.2S, V23.2S
umlal V13.2D, V8.2S, V15.2S
umlal V14.2D, V8.2S, V16.2S
umlal V10.2D, V9.2S, V20.2S
umlal V11.2D, V9.2S, V21.2S
umlal V12.2D, V9.2S, V22.2S
umlal V13.2D, V9.2S, V23.2S
umlal V14.2D, V9.2S, V15.2S
addp D10, V10.2D
addp D11, V11.2D
addp D12, V12.2D
addp D13, V13.2D
addp D14, V14.2D
; Redistribute and handle overflow
usra V11.2D, V10.2D, #26
and V10.16B, V10.16B, V26.16B
usra V14.2D, V13.2D, #26
and V3.16B, V13.16B, V26.16B
ushr V2.2D, V14.2D, #26
usra V12.2D, V11.2D, #26
shl V0.2D, V2.2D, #2
and V1.16B, V11.16B, V26.16B
add V0.2D, V0.2D, V2.2D
and V4.16B, V14.16B, V26.16B
add V10.2D, V10.2D, V0.2D
usra V3.2D, V12.2D, #26
and V2.16B, V12.16B, V26.16B
usra V1.2D, V10.2D, #26
and V0.16B, V10.16B, V26.16B
usra V4.2D, V3.2D, #26
and V3.16B, V3.16B, V26.16B
cmp x2, #0x40
bge L_poly1305_arm64_blocks_loop_64
cmp x2, #16
ble L_poly1305_arm64_blocks_done_32
; Start 32
ld4 {V5.2S, V6.2S, V7.2S, V8.2S}, [x1], #32
sub x2, x2, #32
mov V15.D[0], V15.D[1]
mov V16.D[0], V16.D[1]
mov V17.D[0], V17.D[1]
mov V18.D[0], V18.D[1]
mov V19.D[0], V19.D[1]
mov V20.D[0], V20.D[1]
mov V21.D[0], V21.D[1]
mov V22.D[0], V22.D[1]
mov V23.D[0], V23.D[1]
ushr V9.2S, V8.2S, #8
shl V8.2S, V8.2S, #18
orr V9.8B, V9.8B, V27.8B
sri V8.2S, V7.2S, #14
shl V7.2S, V7.2S, #12
and V8.8B, V8.8B, V25.8B
sri V7.2S, V6.2S, #20
shl V6.2S, V6.2S, #6
and V7.8B, V7.8B, V25.8B
sri V6.2S, V5.2S, #26
and V5.8B, V5.8B, V25.8B
and V6.8B, V6.8B, V25.8B
add V5.2S, V5.2S, V0.2S
add V6.2S, V6.2S, V1.2S
add V7.2S, V7.2S, V2.2S
add V8.2S, V8.2S, V3.2S
add V9.2S, V9.2S, V4.2S
umull V10.2D, V5.2S, V15.2S
umull V11.2D, V5.2S, V16.2S
umull V12.2D, V5.2S, V17.2S
umull V13.2D, V5.2S, V18.2S
umull V14.2D, V5.2S, V19.2S
umlal V10.2D, V6.2S, V23.2S
umlal V11.2D, V6.2S, V15.2S
umlal V12.2D, V6.2S, V16.2S
umlal V13.2D, V6.2S, V17.2S
umlal V14.2D, V6.2S, V18.2S
umlal V10.2D, V7.2S, V22.2S
umlal V11.2D, V7.2S, V23.2S
umlal V12.2D, V7.2S, V15.2S
umlal V13.2D, V7.2S, V16.2S
umlal V14.2D, V7.2S, V17.2S
umlal V10.2D, V8.2S, V21.2S
umlal V11.2D, V8.2S, V22.2S
umlal V12.2D, V8.2S, V23.2S
umlal V13.2D, V8.2S, V15.2S
umlal V14.2D, V8.2S, V16.2S
umlal V10.2D, V9.2S, V20.2S
umlal V11.2D, V9.2S, V21.2S
umlal V12.2D, V9.2S, V22.2S
umlal V13.2D, V9.2S, V23.2S
umlal V14.2D, V9.2S, V15.2S
addp D10, V10.2D
addp D11, V11.2D
addp D12, V12.2D
addp D13, V13.2D
addp D14, V14.2D
; Redistribute and handle overflow
usra V11.2D, V10.2D, #26
and V10.16B, V10.16B, V26.16B
usra V14.2D, V13.2D, #26
and V3.16B, V13.16B, V26.16B
ushr V2.2D, V14.2D, #26
usra V12.2D, V11.2D, #26
shl V0.2D, V2.2D, #2
and V1.16B, V11.16B, V26.16B
add V0.2D, V0.2D, V2.2D
and V4.16B, V14.16B, V26.16B
add V10.2D, V10.2D, V0.2D
usra V3.2D, V12.2D, #26
and V2.16B, V12.16B, V26.16B
usra V1.2D, V10.2D, #26
and V0.16B, V10.16B, V26.16B
usra V4.2D, V3.2D, #26
and V3.16B, V3.16B, V26.16B
L_poly1305_arm64_blocks_done_32
cmp x2, #16
beq L_poly1305_arm64_blocks_transfer
add x14, x0, #0x60
st4 {V0.S, V1.S, V2.S, V3.S}[0], [x14], #16
st1 {V4.S}[0], [x14]
b L_poly1305_arm64_blocks_done_all
L_poly1305_arm64_blocks_transfer
mov w3, V0.S[0]
mov w4, V1.S[0]
mov w5, V2.S[0]
mov w6, V3.S[0]
mov w7, V4.S[0]
b L_poly1305_arm64_blocks_start
L_poly1305_arm64_blocks_done
cmp x2, #16
blt L_poly1305_arm64_blocks_done_all
; Load h
ldp w3, w4, [x0, #96]
ldp w5, w6, [x0, #104]
ldr w7, [x0, #112]
L_poly1305_arm64_blocks_start
mov x17, #1
; Load r
ldp x8, x9, [x0]
; Base26 -> Base 64
add x3, x3, x4, lsl 26
lsr x4, x5, #12
add x3, x3, x5, lsl 52
add x4, x4, x6, lsl 14
lsr x5, x7, #24
add x4, x4, x7, lsl 40
L_poly1305_arm64_blocks_loop
; Load m
ldr x14, [x1]
ldr x15, [x1, #8]
; Add m and !finished at bit 128
adds x3, x3, x14
adcs x4, x4, x15
adc x5, x5, x17
; Multiply h by r
; b[0] * a[0]
mul x10, x8, x3
umulh x11, x8, x3
; b[0] * a[1]
mul x13, x8, x4
umulh x12, x8, x4
; b[1] * a[0]
mul x14, x9, x3
umulh x15, x9, x3
adds x11, x11, x13
; b[1] * a[1]
mul x16, x9, x4
umulh x13, x9, x4
adc x12, x12, x15
adds x11, x11, x14
; b[0] * a[2]
mul x14, x8, x5
adcs x12, x12, x16
; b[1] * a[2]
mul x15, x9, x5
adc x13, x13, xzr
adds x12, x12, x14
adc x13, x13, x15
; Reduce mod 2^130 - 5
; Get high bits
and x14, x12, #-4
; Get top two bits
and x12, x12, #3
; Add top bits * 4
adds x3, x10, x14
; Move down 2 bits
extr x14, x13, x14, #2
adcs x4, x11, x13
lsr x13, x13, #2
adc x5, x12, xzr
; Add top bits.
adds x3, x3, x14
adcs x4, x4, x13
adc x5, x5, xzr
; Sub 16 from length.
subs x2, x2, #16
add x1, x1, #16
; Loop again if more message to do.
bgt L_poly1305_arm64_blocks_loop
extr x7, x5, x4, #40
ubfx x5, x3, #52, #12
ubfx x6, x4, #14, #26
bfi x5, x4, #12, #14
ubfx x4, x3, #26, #26
ubfx x3, x3, #0, #26
stp w3, w4, [x0, #96]
stp w5, w6, [x0, #104]
str w7, [x0, #112]
L_poly1305_arm64_blocks_done_all
ldr x17, [x29, #24]
ldp D8, D9, [x29, #32]
ldp D10, D11, [x29, #48]
ldp D12, D13, [x29, #64]
ldp D14, D15, [x29, #80]
ldp x29, x30, [sp], #0x60
ret
ENDP
AREA |.rodata|, DATA, READONLY, ALIGN=4
ALIGN 8
L_poly1305_set_key_arm64_clamp
DCD 0x0fffffff, 0x0ffffffc, 0x0ffffffc, 0x0ffffffc
AREA |.text|, CODE, READONLY
ALIGN 4
EXPORT poly1305_set_key
poly1305_set_key PROC
stp x29, x30, [sp, #-32]!
add x29, sp, #0
str x17, [x29, #24]
adrp x2, L_poly1305_set_key_arm64_clamp
add x2, x2, L_poly1305_set_key_arm64_clamp
; Load key and pad.
ldp x11, x12, [x1]
ldp x14, x15, [x1, #16]
; Load mask.
ldp x16, x17, [x2]
; Save pad for later
stp x14, x15, [x0, #120]
; Apply clamp.
; r &= 0x0ffffffc0ffffffc0ffffffc0fffffff
and x11, x11, x16
and x12, x12, x17
; Store r - 64-bit version.
stp x11, x12, [x0]
; 128-bits: Base 64 -> Base 26
lsr x7, x12, #40
ubfx x5, x11, #52, #12
ubfx x6, x12, #14, #26
bfi x5, x12, #12, #14
ubfx x4, x11, #26, #26
ubfx x3, x11, #0, #26
stp w3, w4, [x0, #64]
stp w5, w6, [x0, #72]
str w7, [x0, #92]
; Compute r^2
; a[0] * a[0]
mul x3, x11, x11
umulh x4, x11, x11
; 2 * a[0] * a[1]
mul x14, x11, x12
umulh x5, x11, x12
; a[1] * a[1]
mul x15, x12, x12
umulh x6, x12, x12
adds x4, x4, x14, lsl 1
extr x5, x5, x14, #63
adcs x5, x5, x15
adc x6, x6, xzr
; Reduce mod 2^130 - 5
; Get high bits
and x14, x5, #-4
; Get top two bits
and x5, x5, #3
; Add top bits * 4
adds x8, x3, x14
; Move down 2 bits
extr x14, x6, x14, #2
adcs x9, x4, x6
lsr x6, x6, #2
adc x10, x5, xzr
; Add top bits.
adds x8, x8, x14
adcs x9, x9, x6
adc x10, x10, xzr
; 130-bits: Base 64 -> Base 26
extr x7, x10, x9, #40
ubfx x5, x8, #52, #12
ubfx x6, x9, #14, #26
bfi x5, x9, #12, #14
ubfx x4, x8, #26, #26
ubfx x3, x8, #0, #26
stp w3, w4, [x0, #48]
stp w5, w6, [x0, #56]
str w7, [x0, #88]
; Compute r^3
; b[0] * a[0]
mul x3, x11, x8
umulh x4, x11, x8
; b[0] * a[1]
mul x6, x11, x9
umulh x5, x11, x9
; b[1] * a[0]
mul x14, x12, x8
umulh x15, x12, x8
adds x4, x4, x6
; b[1] * a[1]
mul x16, x12, x9
umulh x6, x12, x9
adc x5, x5, x15
adds x4, x4, x14
; b[0] * a[2]
mul x14, x11, x10
adcs x5, x5, x16
; b[1] * a[2]
mul x15, x12, x10
adc x6, x6, xzr
adds x5, x5, x14
adc x6, x6, x15
; Reduce mod 2^130 - 5
; Get high bits
and x14, x5, #-4
; Get top two bits
and x5, x5, #3
; Add top bits * 4
adds x8, x3, x14
; Move down 2 bits
extr x14, x6, x14, #2
adcs x9, x4, x6
lsr x6, x6, #2
adc x10, x5, xzr
; Add top bits.
adds x8, x8, x14
adcs x9, x9, x6
adc x10, x10, xzr
; 130-bits: Base 64 -> Base 26
extr x7, x10, x9, #40
ubfx x5, x8, #52, #12
ubfx x6, x9, #14, #26
bfi x5, x9, #12, #14
ubfx x4, x8, #26, #26
ubfx x3, x8, #0, #26
stp w3, w4, [x0, #32]
stp w5, w6, [x0, #40]
str w7, [x0, #84]
; Compute r^4
; b[0] * a[0]
mul x3, x11, x8
umulh x4, x11, x8
; b[0] * a[1]
mul x6, x11, x9
umulh x5, x11, x9
; b[1] * a[0]
mul x14, x12, x8
umulh x15, x12, x8
adds x4, x4, x6
; b[1] * a[1]
mul x16, x12, x9
umulh x6, x12, x9
adc x5, x5, x15
adds x4, x4, x14
; b[0] * a[2]
mul x14, x11, x10
adcs x5, x5, x16
; b[1] * a[2]
mul x15, x12, x10
adc x6, x6, xzr
adds x5, x5, x14
adc x6, x6, x15
; Reduce mod 2^130 - 5
; Get high bits
and x14, x5, #-4
; Get top two bits
and x5, x5, #3
; Add top bits * 4
adds x11, x3, x14
; Move down 2 bits
extr x14, x6, x14, #2
adcs x12, x4, x6
lsr x6, x6, #2
adc x13, x5, xzr
; Add top bits.
adds x11, x11, x14
adcs x12, x12, x6
adc x13, x13, xzr
; 130-bits: Base 64 -> Base 26
extr x7, x13, x12, #40
ubfx x5, x11, #52, #12
ubfx x6, x12, #14, #26
bfi x5, x12, #12, #14
ubfx x4, x11, #26, #26
ubfx x3, x11, #0, #26
stp w3, w4, [x0, #16]
stp w5, w6, [x0, #24]
str w7, [x0, #80]
; h (accumulator) = 0
stp xzr, xzr, [x0, #96]
str wzr, [x0, #112]
; Zero leftover
str xzr, [x0, #136]
; Zero finished
strb wzr, [x0, #160]
ldr x17, [x29, #24]
ldp x29, x30, [sp], #32
ret
ENDP
AREA |.text|, CODE, READONLY
ALIGN 4
EXPORT poly1305_final
poly1305_final PROC
ldp x8, x9, [x0, #120]
ldp w2, w3, [x0, #96]
ldp w4, w5, [x0, #104]
ldr w6, [x0, #112]
add x2, x2, x3, lsl 26
lsr x3, x4, #12
add x2, x2, x4, lsl 52
add x3, x3, x5, lsl 14
lsr x4, x6, #24
add x3, x3, x6, lsl 40
; Add 5 to h.
adds x5, x2, #5
adcs x6, x3, xzr
adc x7, x4, xzr
; Check if h+5 s larger than p.
cmp x7, #3
csel x2, x5, x2, hi
csel x3, x6, x3, hi
; Add padding
adds x2, x2, x8
adc x3, x3, x9
; Store MAC
stp x2, x3, [x1]
; Zero out h.
stp xzr, xzr, [x0, #96]
str wzr, [x0, #112]
; Zero out r64.
stp xzr, xzr, [x0]
; Zero out r.
stp xzr, xzr, [x0, #16]
; Zero out r_2.
stp xzr, xzr, [x0, #48]
str xzr, [x0, #64]
; Zero out r_4.
stp xzr, xzr, [x0, #16]
str xzr, [x0, #32]
; Zero out pad.
stp xzr, xzr, [x0, #120]
ret
ENDP
END

1193
wolfcrypt/src/port/arm/armv8-sha256-asm.asm Normal file
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File diff suppressed because it is too large Load Diff

370
wolfcrypt/src/port/arm/armv8-sha3-asm.asm Normal file
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@@ -0,0 +1,370 @@
; /* armv8-sha3-asm
; *
; * Copyright (C) 2006-2026 wolfSSL Inc.
; *
; * This file is part of wolfSSL.
; *
; * wolfSSL is free software; you can redistribute it and/or modify
; * it under the terms of the GNU General Public License as published by
; * the Free Software Foundation; either version 3 of the License, or
; * (at your option) any later version.
; *
; * wolfSSL is distributed in the hope that it will be useful,
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; * GNU General Public License for more details.
; *
; * You should have received a copy of the GNU General Public License
; * along with this program; if not, write to the Free Software
; * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
; */
; Generated using (from wolfssl):
; cd ../scripts
; ruby ./sha3/sha3.rb arm64 \
; ../wolfssl/wolfcrypt/src/port/arm/armv8-sha3-asm.asm
IF :DEF:WOLFSSL_SHA3
IF :DEF:WOLFSSL_ARMASM_CRYPTO_SHA3
AREA |.rodata|, DATA, READONLY, ALIGN=4
ALIGN 16
L_SHA3_transform_crypto_r
DCQ 0x0000000000000001, 0x0000000000008082
DCQ 0x800000000000808a, 0x8000000080008000
DCQ 0x000000000000808b, 0x0000000080000001
DCQ 0x8000000080008081, 0x8000000000008009
DCQ 0x000000000000008a, 0x0000000000000088
DCQ 0x0000000080008009, 0x000000008000000a
DCQ 0x000000008000808b, 0x800000000000008b
DCQ 0x8000000000008089, 0x8000000000008003
DCQ 0x8000000000008002, 0x8000000000000080
DCQ 0x000000000000800a, 0x800000008000000a
DCQ 0x8000000080008081, 0x8000000000008080
DCQ 0x0000000080000001, 0x8000000080008008
AREA |.text|, CODE, READONLY
ALIGN 4
EXPORT BlockSha3_crypto
BlockSha3_crypto PROC
stp x29, x30, [sp, #-80]!
add x29, sp, #0
stp D8, D9, [x29, #16]
stp D10, D11, [x29, #32]
stp D12, D13, [x29, #48]
stp D14, D15, [x29, #64]
adrp x1, L_SHA3_transform_crypto_r
add x1, x1, L_SHA3_transform_crypto_r
; .arch_extension sha3
ld4 {V0.D, V1.D, V2.D, V3.D}[0], [x0], #32
ld4 {V4.D, V5.D, V6.D, V7.D}[0], [x0], #32
ld4 {V8.D, V9.D, V10.D, V11.D}[0], [x0], #32
ld4 {V12.D, V13.D, V14.D, V15.D}[0], [x0], #32
ld4 {V16.D, V17.D, V18.D, V19.D}[0], [x0], #32
ld4 {V20.D, V21.D, V22.D, V23.D}[0], [x0], #32
ld1 {V24.1D}, [x0]
sub x0, x0, #0xc0
mov x2, #24
; Start of 24 rounds
L_sha3_crypto_begin
; Col Mix
eor3 V31.16B, V0.16B, V5.16B, V10.16B
eor3 V27.16B, V1.16B, V6.16B, V11.16B
eor3 V28.16B, V2.16B, V7.16B, V12.16B
eor3 V29.16B, V3.16B, V8.16B, V13.16B
eor3 V30.16B, V4.16B, V9.16B, V14.16B
eor3 V31.16B, V31.16B, V15.16B, V20.16B
eor3 V27.16B, V27.16B, V16.16B, V21.16B
eor3 V28.16B, V28.16B, V17.16B, V22.16B
eor3 V29.16B, V29.16B, V18.16B, V23.16B
eor3 V30.16B, V30.16B, V19.16B, V24.16B
rax1 V25.2D, V30.2D, V27.2D
rax1 V26.2D, V31.2D, V28.2D
rax1 V27.2D, V27.2D, V29.2D
rax1 V28.2D, V28.2D, V30.2D
rax1 V29.2D, V29.2D, V31.2D
eor V0.16B, V0.16B, V25.16B
xar V30.2D, V1.2D, V26.2D, #63
xar V1.2D, V6.2D, V26.2D, #20
xar V6.2D, V9.2D, V29.2D, #44
xar V9.2D, V22.2D, V27.2D, #3
xar V22.2D, V14.2D, V29.2D, #25
xar V14.2D, V20.2D, V25.2D, #46
xar V20.2D, V2.2D, V27.2D, #2
xar V2.2D, V12.2D, V27.2D, #21
xar V12.2D, V13.2D, V28.2D, #39
xar V13.2D, V19.2D, V29.2D, #56
xar V19.2D, V23.2D, V28.2D, #8
xar V23.2D, V15.2D, V25.2D, #23
xar V15.2D, V4.2D, V29.2D, #37
xar V4.2D, V24.2D, V29.2D, #50
xar V24.2D, V21.2D, V26.2D, #62
xar V21.2D, V8.2D, V28.2D, #9
xar V8.2D, V16.2D, V26.2D, #19
xar V16.2D, V5.2D, V25.2D, #28
xar V5.2D, V3.2D, V28.2D, #36
xar V3.2D, V18.2D, V28.2D, #43
xar V18.2D, V17.2D, V27.2D, #49
xar V17.2D, V11.2D, V26.2D, #54
xar V11.2D, V7.2D, V27.2D, #58
xar V7.2D, V10.2D, V25.2D, #61
; Row Mix
mov V25.16B, V0.16B
mov V26.16B, V1.16B
bcax V0.16B, V25.16B, V2.16B, V26.16B
bcax V1.16B, V26.16B, V3.16B, V2.16B
bcax V2.16B, V2.16B, V4.16B, V3.16B
bcax V3.16B, V3.16B, V25.16B, V4.16B
bcax V4.16B, V4.16B, V26.16B, V25.16B
mov V25.16B, V5.16B
mov V26.16B, V6.16B
bcax V5.16B, V25.16B, V7.16B, V26.16B
bcax V6.16B, V26.16B, V8.16B, V7.16B
bcax V7.16B, V7.16B, V9.16B, V8.16B
bcax V8.16B, V8.16B, V25.16B, V9.16B
bcax V9.16B, V9.16B, V26.16B, V25.16B
mov V26.16B, V11.16B
bcax V10.16B, V30.16B, V12.16B, V26.16B
bcax V11.16B, V26.16B, V13.16B, V12.16B
bcax V12.16B, V12.16B, V14.16B, V13.16B
bcax V13.16B, V13.16B, V30.16B, V14.16B
bcax V14.16B, V14.16B, V26.16B, V30.16B
mov V25.16B, V15.16B
mov V26.16B, V16.16B
bcax V15.16B, V25.16B, V17.16B, V26.16B
bcax V16.16B, V26.16B, V18.16B, V17.16B
bcax V17.16B, V17.16B, V19.16B, V18.16B
bcax V18.16B, V18.16B, V25.16B, V19.16B
bcax V19.16B, V19.16B, V26.16B, V25.16B
mov V25.16B, V20.16B
mov V26.16B, V21.16B
bcax V20.16B, V25.16B, V22.16B, V26.16B
bcax V21.16B, V26.16B, V23.16B, V22.16B
bcax V22.16B, V22.16B, V24.16B, V23.16B
bcax V23.16B, V23.16B, V25.16B, V24.16B
bcax V24.16B, V24.16B, V26.16B, V25.16B
ld1r {V30.2D}, [x1], #8
subs x2, x2, #1
eor V0.16B, V0.16B, V30.16B
bne L_sha3_crypto_begin
st4 {V0.D, V1.D, V2.D, V3.D}[0], [x0], #32
st4 {V4.D, V5.D, V6.D, V7.D}[0], [x0], #32
st4 {V8.D, V9.D, V10.D, V11.D}[0], [x0], #32
st4 {V12.D, V13.D, V14.D, V15.D}[0], [x0], #32
st4 {V16.D, V17.D, V18.D, V19.D}[0], [x0], #32
st4 {V20.D, V21.D, V22.D, V23.D}[0], [x0], #32
st1 {V24.1D}, [x0]
ldp D8, D9, [x29, #16]
ldp D10, D11, [x29, #32]
ldp D12, D13, [x29, #48]
ldp D14, D15, [x29, #64]
ldp x29, x30, [sp], #0x50
ret
ENDP
ENDIF
AREA |.rodata|, DATA, READONLY, ALIGN=4
ALIGN 16
L_SHA3_transform_base_r
DCQ 0x0000000000000001, 0x0000000000008082
DCQ 0x800000000000808a, 0x8000000080008000
DCQ 0x000000000000808b, 0x0000000080000001
DCQ 0x8000000080008081, 0x8000000000008009
DCQ 0x000000000000008a, 0x0000000000000088
DCQ 0x0000000080008009, 0x000000008000000a
DCQ 0x000000008000808b, 0x800000000000008b
DCQ 0x8000000000008089, 0x8000000000008003
DCQ 0x8000000000008002, 0x8000000000000080
DCQ 0x000000000000800a, 0x800000008000000a
DCQ 0x8000000080008081, 0x8000000000008080
DCQ 0x0000000080000001, 0x8000000080008008
AREA |.text|, CODE, READONLY
ALIGN 4
EXPORT BlockSha3_base
BlockSha3_base PROC
stp x29, x30, [sp, #-160]!
add x29, sp, #0
stp x17, x19, [x29, #72]
stp x20, x21, [x29, #88]
stp x22, x23, [x29, #104]
stp x24, x25, [x29, #120]
stp x26, x27, [x29, #136]
str x28, [x29, #152]
adrp x27, L_SHA3_transform_base_r
add x27, x27, L_SHA3_transform_base_r
ldp x1, x2, [x0]
ldp x3, x4, [x0, #16]
ldp x5, x6, [x0, #32]
ldp x7, x8, [x0, #48]
ldp x9, x10, [x0, #64]
ldp x11, x12, [x0, #80]
ldp x13, x14, [x0, #96]
ldp x15, x16, [x0, #112]
ldp x17, x19, [x0, #128]
ldp x20, x21, [x0, #144]
ldp x22, x23, [x0, #160]
ldp x24, x25, [x0, #176]
ldr x26, [x0, #192]
str x0, [x29, #40]
mov x28, #24
; Start of 24 rounds
L_SHA3_transform_base_begin
stp x27, x28, [x29, #48]
eor x0, x5, x10
eor x30, x1, x6
eor x28, x3, x8
eor x0, x0, x15
eor x30, x30, x11
eor x28, x28, x13
eor x0, x0, x21
eor x30, x30, x16
eor x28, x28, x19
eor x0, x0, x26
eor x30, x30, x22
eor x28, x28, x24
str x0, [x29, #32]
str x28, [x29, #24]
eor x27, x2, x7
eor x28, x4, x9
eor x27, x27, x12
eor x28, x28, x14
eor x27, x27, x17
eor x28, x28, x20
eor x27, x27, x23
eor x28, x28, x25
eor x0, x0, x27, ror 63
eor x27, x27, x28, ror 63
eor x1, x1, x0
eor x6, x6, x0
eor x11, x11, x0
eor x16, x16, x0
eor x22, x22, x0
eor x3, x3, x27
eor x8, x8, x27
eor x13, x13, x27
eor x19, x19, x27
eor x24, x24, x27
ldr x0, [x29, #32]
ldr x27, [x29, #24]
eor x28, x28, x30, ror 63
eor x30, x30, x27, ror 63
eor x27, x27, x0, ror 63
eor x5, x5, x28
eor x10, x10, x28
eor x15, x15, x28
eor x21, x21, x28
eor x26, x26, x28
eor x2, x2, x30
eor x7, x7, x30
eor x12, x12, x30
eor x17, x17, x30
eor x23, x23, x30
eor x4, x4, x27
eor x9, x9, x27
eor x14, x14, x27
eor x20, x20, x27
eor x25, x25, x27
; Swap Rotate
ror x0, x2, #63
ror x2, x7, #20
ror x7, x10, #44
ror x10, x24, #3
ror x24, x15, #25
ror x15, x22, #46
ror x22, x3, #2
ror x3, x13, #21
ror x13, x14, #39
ror x14, x21, #56
ror x21, x25, #8
ror x25, x16, #23
ror x16, x5, #37
ror x5, x26, #50
ror x26, x23, #62
ror x23, x9, #9
ror x9, x17, #19
ror x17, x6, #28
ror x6, x4, #36
ror x4, x20, #43
ror x20, x19, #49
ror x19, x12, #54
ror x12, x8, #58
ror x8, x11, #61
; Row Mix
bic x11, x3, x2
bic x27, x4, x3
bic x28, x1, x5
bic x30, x2, x1
eor x1, x1, x11
eor x2, x2, x27
bic x11, x5, x4
eor x4, x4, x28
eor x3, x3, x11
eor x5, x5, x30
bic x11, x8, x7
bic x27, x9, x8
bic x28, x6, x10
bic x30, x7, x6
eor x6, x6, x11
eor x7, x7, x27
bic x11, x10, x9
eor x9, x9, x28
eor x8, x8, x11
eor x10, x10, x30
bic x11, x13, x12
bic x27, x14, x13
bic x28, x0, x15
bic x30, x12, x0
eor x11, x0, x11
eor x12, x12, x27
bic x0, x15, x14
eor x14, x14, x28
eor x13, x13, x0
eor x15, x15, x30
bic x0, x19, x17
bic x27, x20, x19
bic x28, x16, x21
bic x30, x17, x16
eor x16, x16, x0
eor x17, x17, x27
bic x0, x21, x20
eor x20, x20, x28
eor x19, x19, x0
eor x21, x21, x30
bic x0, x24, x23
bic x27, x25, x24
bic x28, x22, x26
bic x30, x23, x22
eor x22, x22, x0
eor x23, x23, x27
bic x0, x26, x25
eor x25, x25, x28
eor x24, x24, x0
eor x26, x26, x30
; Done transforming
ldp x27, x28, [x29, #48]
ldr x0, [x27], #8
subs x28, x28, #1
eor x1, x1, x0
bne L_SHA3_transform_base_begin
ldr x0, [x29, #40]
stp x1, x2, [x0]
stp x3, x4, [x0, #16]
stp x5, x6, [x0, #32]
stp x7, x8, [x0, #48]
stp x9, x10, [x0, #64]
stp x11, x12, [x0, #80]
stp x13, x14, [x0, #96]
stp x15, x16, [x0, #112]
stp x17, x19, [x0, #128]
stp x20, x21, [x0, #144]
stp x22, x23, [x0, #160]
stp x24, x25, [x0, #176]
str x26, [x0, #192]
ldp x17, x19, [x29, #72]
ldp x20, x21, [x29, #88]
ldp x22, x23, [x29, #104]
ldp x24, x25, [x29, #120]
ldp x26, x27, [x29, #136]
ldr x28, [x29, #152]
ldp x29, x30, [sp], #0xa0
ret
ENDP
ENDIF
END

1571
wolfcrypt/src/port/arm/armv8-sha512-asm.asm Normal file
View File

File diff suppressed because it is too large Load Diff

160
wolfcrypt/src/wc_mldsa_asm.asm
View File

@@ -27314,6 +27314,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27398,6 +27400,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27482,6 +27486,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27566,6 +27572,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27650,6 +27658,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27734,6 +27744,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27818,6 +27830,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27902,6 +27916,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27986,6 +28002,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28070,6 +28088,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28154,6 +28174,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28238,6 +28260,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28322,6 +28346,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28406,6 +28432,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28490,6 +28518,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28574,6 +28604,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28659,6 +28691,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28743,6 +28777,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28827,6 +28863,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28911,6 +28949,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28995,6 +29035,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29079,6 +29121,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29163,6 +29207,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29247,6 +29293,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29331,6 +29379,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29415,6 +29465,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29499,6 +29551,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29583,6 +29637,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29667,6 +29723,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29751,6 +29809,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29835,6 +29895,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29919,6 +29981,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30004,6 +30068,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30088,6 +30154,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30172,6 +30240,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30256,6 +30326,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30340,6 +30412,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30424,6 +30498,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30508,6 +30584,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30592,6 +30670,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30676,6 +30756,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30760,6 +30842,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30844,6 +30928,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30928,6 +31014,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31012,6 +31100,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31096,6 +31186,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31180,6 +31272,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31264,6 +31358,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31349,6 +31445,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31433,6 +31531,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31517,6 +31617,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31601,6 +31703,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31685,6 +31789,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31769,6 +31875,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31853,6 +31961,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31937,6 +32047,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32021,6 +32133,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32105,6 +32219,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32189,6 +32305,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32273,6 +32391,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32357,6 +32477,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32441,6 +32563,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32525,6 +32649,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32609,6 +32735,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32779,6 +32907,8 @@ L_mldsa_use_hint_32_avx2_hints_done__0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32851,6 +32981,8 @@ L_mldsa_use_hint_32_avx2_hints_done__1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32923,6 +33055,8 @@ L_mldsa_use_hint_32_avx2_hints_done__2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32995,6 +33129,8 @@ L_mldsa_use_hint_32_avx2_hints_done__3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33067,6 +33203,8 @@ L_mldsa_use_hint_32_avx2_hints_done__4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33139,6 +33277,8 @@ L_mldsa_use_hint_32_avx2_hints_done__5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33211,6 +33351,8 @@ L_mldsa_use_hint_32_avx2_hints_done__6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33283,6 +33425,8 @@ L_mldsa_use_hint_32_avx2_hints_done__7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33355,6 +33499,8 @@ L_mldsa_use_hint_32_avx2_hints_done__8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33427,6 +33573,8 @@ L_mldsa_use_hint_32_avx2_hints_done__9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33499,6 +33647,8 @@ L_mldsa_use_hint_32_avx2_hints_done__10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33571,6 +33721,8 @@ L_mldsa_use_hint_32_avx2_hints_done__11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33643,6 +33795,8 @@ L_mldsa_use_hint_32_avx2_hints_done__12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33715,6 +33869,8 @@ L_mldsa_use_hint_32_avx2_hints_done__13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33787,6 +33943,8 @@ L_mldsa_use_hint_32_avx2_hints_done__14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33859,6 +34017,8 @@ L_mldsa_use_hint_32_avx2_hints_done__15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1

67
wolfssl-VS2022.vcxproj
View File

@@ -64,6 +64,20 @@
msbuild /p:WolfSSLIntelAsm=true -->
<WolfSSLIntelAsm Condition="'$(WolfSSLIntelAsm)'==''">false</WolfSSLIntelAsm>
</PropertyGroup>
<PropertyGroup Label="WolfSSLAarch64Asm">
<!-- Build the ARMv8 (AArch64) crypto assembly (AES / SHA-2 / SHA-3 /
Curve25519 / Ed25519 / Poly1305 / ChaCha / ML-KEM) with armasm64 and
enable the matching WOLFSSL_ARMASM code paths. Off by default (pure
C). Enable on an ARM64 build with:
msbuild /p:WolfSSLAarch64Asm=true -->
<WolfSSLAarch64Asm Condition="'$(WolfSSLAarch64Asm)'==''">false</WolfSSLAarch64Asm>
<!-- Feature macros the .asm files are guarded by. These must mirror the
feature set enabled for the C compile (see IDE/WIN/user_settings.h and
the WOLFSSL_ARMASM* defines below); a symbol that is left undefined
here simply drops the matching assembly (safe - the C caller then uses
a C fallback), while a symbol enabled here but not in C is dead code. -->
<WolfSSLArmAsmDefs>-PreDefine "HAVE_AES_CBC SETL {TRUE}" -PreDefine "HAVE_AESCCM SETL {TRUE}" -PreDefine "HAVE_AESGCM SETL {TRUE}" -PreDefine "HAVE_AES_ECB SETL {TRUE}" -PreDefine "HAVE_AES_DECRYPT SETL {TRUE}" -PreDefine "WOLFSSL_AES_COUNTER SETL {TRUE}" -PreDefine "WOLFSSL_AES_DIRECT SETL {TRUE}" -PreDefine "WOLFSSL_AES_XTS SETL {TRUE}" -PreDefine "WOLFSSL_AESGCM_STREAM SETL {TRUE}" -PreDefine "WOLFSSL_SHA224 SETL {TRUE}" -PreDefine "WOLFSSL_SHA3 SETL {TRUE}" -PreDefine "WOLFSSL_ARMASM_CRYPTO_SHA3 SETL {TRUE}" -PreDefine "WOLFSSL_SHA384 SETL {TRUE}" -PreDefine "WOLFSSL_SHA512 SETL {TRUE}" -PreDefine "WOLFSSL_ARMASM_CRYPTO_SHA512 SETL {TRUE}" -PreDefine "HAVE_CHACHA SETL {TRUE}" -PreDefine "HAVE_CURVE25519 SETL {TRUE}" -PreDefine "HAVE_ED25519 SETL {TRUE}" -PreDefine "WOLFSSL_HAVE_MLKEM SETL {TRUE}"</WolfSSLArmAsmDefs>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
<ConfigurationType>StaticLibrary</ConfigurationType>
<PlatformToolset>v143</PlatformToolset>
@@ -639,6 +653,54 @@
<Command Condition="'$(WolfSSLIntelAsm)'=='true' And '$(Platform)'=='x64'">ml64.exe /c /Zi /DWOLFSSL_X86_64_BUILD /DWOLFSSL_HAVE_MLKEM /DWOLFSSL_HAVE_MLDSA /DWOLFSSL_HAVE_SLHDSA /DHAVE_ED25519 /Fo"$(IntDir)%(Filename).obj" %(Identity)</Command>
<Outputs Condition="'$(WolfSSLIntelAsm)'=='true' And '$(Platform)'=='x64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-aes-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-chacha-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-curve25519.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-mlkem-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-poly1305-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-sha256-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-sha3-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-sha512-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<ClInclude Include="IDE\WIN\user_settings.h" />
</ItemGroup>
<ItemGroup>
@@ -656,6 +718,11 @@
<PreprocessorDefinitions>USE_INTEL_SPEEDUP;WOLFSSL_X86_64_BUILD;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<ItemDefinitionGroup Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">
<ClCompile>
<PreprocessorDefinitions>WOLFSSL_ARMASM;WOLFSSL_ARMASM_CRYPTO_SHA3;WOLFSSL_ARMASM_CRYPTO_SHA512;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

67
wolfssl.vcxproj
View File

@@ -63,6 +63,20 @@
msbuild /p:WolfSSLIntelAsm=true -->
<WolfSSLIntelAsm Condition="'$(WolfSSLIntelAsm)'==''">false</WolfSSLIntelAsm>
</PropertyGroup>
<PropertyGroup Label="WolfSSLAarch64Asm">
<!-- Build the ARMv8 (AArch64) crypto assembly (AES / SHA-2 / SHA-3 /
Curve25519 / Ed25519 / Poly1305 / ChaCha / ML-KEM) with armasm64 and
enable the matching WOLFSSL_ARMASM code paths. Off by default (pure
C). Enable on an ARM64 build with:
msbuild /p:WolfSSLAarch64Asm=true -->
<WolfSSLAarch64Asm Condition="'$(WolfSSLAarch64Asm)'==''">false</WolfSSLAarch64Asm>
<!-- Feature macros the .asm files are guarded by. These must mirror the
feature set enabled for the C compile (see IDE/WIN/user_settings.h and
the WOLFSSL_ARMASM* defines below); a symbol that is left undefined
here simply drops the matching assembly (safe - the C caller then uses
a C fallback), while a symbol enabled here but not in C is dead code. -->
<WolfSSLArmAsmDefs>-PreDefine "HAVE_AES_CBC SETL {TRUE}" -PreDefine "HAVE_AESCCM SETL {TRUE}" -PreDefine "HAVE_AESGCM SETL {TRUE}" -PreDefine "HAVE_AES_ECB SETL {TRUE}" -PreDefine "HAVE_AES_DECRYPT SETL {TRUE}" -PreDefine "WOLFSSL_AES_COUNTER SETL {TRUE}" -PreDefine "WOLFSSL_AES_DIRECT SETL {TRUE}" -PreDefine "WOLFSSL_AES_XTS SETL {TRUE}" -PreDefine "WOLFSSL_AESGCM_STREAM SETL {TRUE}" -PreDefine "WOLFSSL_SHA224 SETL {TRUE}" -PreDefine "WOLFSSL_SHA3 SETL {TRUE}" -PreDefine "WOLFSSL_ARMASM_CRYPTO_SHA3 SETL {TRUE}" -PreDefine "WOLFSSL_SHA384 SETL {TRUE}" -PreDefine "WOLFSSL_SHA512 SETL {TRUE}" -PreDefine "WOLFSSL_ARMASM_CRYPTO_SHA512 SETL {TRUE}" -PreDefine "HAVE_CHACHA SETL {TRUE}" -PreDefine "HAVE_CURVE25519 SETL {TRUE}" -PreDefine "HAVE_ED25519 SETL {TRUE}" -PreDefine "WOLFSSL_HAVE_MLKEM SETL {TRUE}"</WolfSSLArmAsmDefs>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
<ConfigurationType>StaticLibrary</ConfigurationType>
<PlatformToolset>v110</PlatformToolset>
@@ -639,6 +653,54 @@
<Command Condition="'$(WolfSSLIntelAsm)'=='true' And '$(Platform)'=='x64'">ml64.exe /c /Zi /DWOLFSSL_X86_64_BUILD /DWOLFSSL_HAVE_MLKEM /DWOLFSSL_HAVE_MLDSA /DWOLFSSL_HAVE_SLHDSA /DHAVE_ED25519 /Fo"$(IntDir)%(Filename).obj" %(Identity)</Command>
<Outputs Condition="'$(WolfSSLIntelAsm)'=='true' And '$(Platform)'=='x64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-aes-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-chacha-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-curve25519.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-mlkem-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-poly1305-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-sha256-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-sha3-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<CustomBuild Include="wolfcrypt\src\port\arm\armv8-sha512-asm.asm">
<ExcludedFromBuild>true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">false</ExcludedFromBuild>
<Command Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">armasm64.exe -o "$(IntDir)%(Filename).obj" $(WolfSSLArmAsmDefs) %(Identity)</Command>
<Outputs Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">$(IntDir)%(Filename).obj</Outputs>
</CustomBuild>
<ClInclude Include="IDE\WIN\user_settings.h" />
</ItemGroup>
<ItemGroup>
@@ -656,6 +718,11 @@
<PreprocessorDefinitions>USE_INTEL_SPEEDUP;WOLFSSL_X86_64_BUILD;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<ItemDefinitionGroup Condition="'$(WolfSSLAarch64Asm)'=='true' And '$(Platform)'=='ARM64'">
<ClCompile>
<PreprocessorDefinitions>WOLFSSL_ARMASM;WOLFSSL_ARMASM_CRYPTO_SHA3;WOLFSSL_ARMASM_CRYPTO_SHA512;%(PreprocessorDefinitions)</PreprocessorDefinitions>
</ClCompile>
</ItemDefinitionGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

9
wolfssl/wolfcrypt/settings.h
View File

@@ -380,6 +380,15 @@
#endif
#endif
/* Microsoft's ARM64 compiler defines _M_ARM64 but not __aarch64__. The wolfSSL
* ARMv8 assembly (WOLFSSL_ARMASM) and all of its C callers are gated on
* __aarch64__, so map _M_ARM64 across when building that assembly with MSVC and
* armasm64. Scoped to WOLFSSL_ARMASM so a plain MSVC ARM64 (pure C) build is
* left untouched. */
#if defined(_M_ARM64) && defined(WOLFSSL_ARMASM) && !defined(__aarch64__)
#define __aarch64__ 1
#endif
/* Forward propagation of the legacy parent gate to the canonical name
* (HAVE_DILITHIUM -> WOLFSSL_HAVE_MLDSA). Always active: required so that
* a user_settings.h or build flag using only the legacy spelling still

4
wolfssl/wolfcrypt/wc_port.h
View File

@@ -1949,6 +1949,10 @@ WOLFSSL_ABI WOLFSSL_API int wolfCrypt_Cleanup(void);
#define XFENCE() XASM_VOLATILE("lfence")
#elif defined (__arm__) && (__ARM_ARCH > 6)
#define XFENCE() XASM_VOLATILE("isb")
#elif defined(_MSC_VER) && defined(_M_ARM64)
/* MSVC on ARM64 has no __asm__; use the ISB intrinsic barrier. */
#include <intrin.h>
#define XFENCE() __isb(_ARM64_BARRIER_SY)
#elif defined(__aarch64__)
/* Change ".inst 0xd50330ff" to "sb" when compilers support it. */
#ifdef WOLFSSL_ARMASM_BARRIER_SB