mirror of
https://github.com/Optiboot/optiboot.git
synced 2025-08-17 21:41:03 +03:00
More 14/20 bit chip defintions.
Mostly, struggling with IDEs :-(
This commit is contained in:
@@ -127,7 +127,7 @@
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#define OPTIBOOT_CUSTOMVER 0
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#define OPTIBOOT_CUSTOMVER 0
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#endif
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#endif
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unsigned const int __attribute__((section(".version")))
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unsigned const int __attribute__((section(".version"))) __attribute__((used))
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optiboot_version = 256*(OPTIBOOT_MAJVER + OPTIBOOT_CUSTOMVER) + OPTIBOOT_MINVER;
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optiboot_version = 256*(OPTIBOOT_MAJVER + OPTIBOOT_CUSTOMVER) + OPTIBOOT_MINVER;
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@@ -135,13 +135,13 @@ optiboot_version = 256*(OPTIBOOT_MAJVER + OPTIBOOT_CUSTOMVER) + OPTIBOOT_MINVER;
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#include <avr/io.h>
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#include <avr/io.h>
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FUSES = {
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FUSES = {
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// .WDTCFG, /* Watchdog Configuration */
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.WDTCFG = 0, /* Watchdog Configuration */
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// .BODCFG, /* BOD Configuration */
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.BODCFG = FUSE_BODCFG_DEFAULT, /* BOD Configuration */
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.OSCCFG = 2, /* Oscillator Configuration */
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.TCD0CFG = FUSE_TCD0CFG_DEFAULT, /* TCD0 Configuration */
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// .TCD0CFG, /* TCD0 Configuration */
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.OSCCFG = 2, /* 20MHz */
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.SYSCFG0 = 0xC8, /* RESET is active */
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.SYSCFG0 = 0xC4, /* RESET is not yet */
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.SYSCFG1 = 0x06, /* startup 32ms */
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.SYSCFG1 = 0x06, /* startup 32ms */
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// .APPEND = 0, /* Application Code Section End */
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.APPEND = 0, /* Application Code Section End */
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.BOOTEND = 2 /* Boot Section End */
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.BOOTEND = 2 /* Boot Section End */
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};
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};
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@@ -296,8 +296,8 @@ int main (void) {
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* and still skip bootloader if not necessary
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* and still skip bootloader if not necessary
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*/
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*/
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ch = RSTCTRL.RSTFR;
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ch = RSTCTRL.RSTFR;
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RSTCTRL.RSTFR = ch; // reset causes, for now.
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// RSTCTRL.RSTFR = ch; // reset causes, for now.
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ch &= ~RSTCTRL_UPDIRF_bm; // clear "reset by UPDI."
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// Skip all logic and run bootloader if cause is cleared (application request)
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// Skip all logic and run bootloader if cause is cleared (application request)
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if (ch != 0) {
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if (ch != 0) {
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/*
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/*
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@@ -350,8 +350,8 @@ int main (void) {
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MYUART.CTRLA = 0; // Interrupts: all off
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MYUART.CTRLA = 0; // Interrupts: all off
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MYUART.CTRLB = USART_RXEN_bm | USART_TXEN_bm;
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MYUART.CTRLB = USART_RXEN_bm | USART_TXEN_bm;
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// Set up watchdog to trigger after 8s
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// Set up watchdog to trigger after 1s
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watchdogConfig(WDT_PERIOD_8KCLK_gc);
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watchdogConfig(WDT_PERIOD_1KCLK_gc);
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#if (LED_START_FLASHES > 0) || defined(LED_DATA_FLASH) || defined(LED_START_ON)
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#if (LED_START_FLASHES > 0) || defined(LED_DATA_FLASH) || defined(LED_START_ON)
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/* Set LED pin as output */
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/* Set LED pin as output */
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@@ -535,6 +535,7 @@ void flash_led (uint8_t count) {
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return;
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return;
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}
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}
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}
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}
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watchdogReset(); // for breakpointing
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}
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}
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#endif
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#endif
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@@ -636,6 +637,7 @@ void app()
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ch = RSTCTRL.RSTFR;
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ch = RSTCTRL.RSTFR;
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RSTCTRL.RSTFR = ch; // reset causes
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RSTCTRL.RSTFR = ch; // reset causes
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__asm__ __volatile__ ("jmp 0"); // similar to running off end of memory
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_PROTECTED_WRITE(RSTCTRL.SWRR, 1); // cause new reset
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_PROTECTED_WRITE(RSTCTRL.SWRR, 1); // cause new reset
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for (long i=0; i < 1000000; i++) {
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for (long i=0; i < 1000000; i++) {
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__asm__ __volatile__("wdr");
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__asm__ __volatile__("wdr");
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@@ -759,10 +759,15 @@
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#endif // Tiny402/etc
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#endif // Tiny402/etc
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/*
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/*
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* 14pin Tiny0, Tiny1
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* 14pin and 20pin Tiny0, Tiny1
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* The 14 and 20pin packages both conveniently have the UART on the
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* same port pins, and the same pinmux structure!
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*/
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*/
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#if defined(__ATtiny1614__) || defined(__ATtiny1604__) || \
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#if defined(__AVR_ATtiny1614__) || defined(__AVR_ATtiny1604__) || \
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defined(__ATtiny814__) || defined(__ATtiny804__)
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defined(__AVR_ATtiny814__) || defined(__AVR_ATtiny804__) || \
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defined(__AVR_ATtiny1606__) || defined(__AVR_ATtiny806__) || \
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defined(__AVR_ATtiny406__) || defined(__AVR_ATtiny3216__) || \
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defined(__AVR_ATtiny816__) || defined(__AVR_ATtiny416__)
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#define MYPMUX PORTMUX.CTRLB
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#define MYPMUX PORTMUX.CTRLB
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# if (UARTTX == B2)
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# if (UARTTX == B2)
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# ifndef USART0
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# ifndef USART0
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@@ -782,10 +787,6 @@
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# endif
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# endif
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#endif
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#endif
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#if defined(__ATtiny3216__) || defined(__ATtiny1606__)
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#endif
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#ifndef MYUART
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#ifndef MYUART
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# warning No UARTTX pin specified.
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# warning No UARTTX pin specified.
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#endif
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#endif
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