From adafe79832d4fd25c7d6ff09976259e04dce73b7 Mon Sep 17 00:00:00 2001 From: WestfW Date: Fri, 6 Sep 2019 01:06:24 -0700 Subject: [PATCH] More 14/20 bit chip defintions. Mostly, struggling with IDEs :-( --- optiboot/bootloaders/optiboot/optiboot_x.c | 24 ++++++++++++---------- optiboot/bootloaders/optiboot/pin_defs_x.h | 15 +++++++------- 2 files changed, 21 insertions(+), 18 deletions(-) diff --git a/optiboot/bootloaders/optiboot/optiboot_x.c b/optiboot/bootloaders/optiboot/optiboot_x.c index 3e8a3c2..f882de5 100644 --- a/optiboot/bootloaders/optiboot/optiboot_x.c +++ b/optiboot/bootloaders/optiboot/optiboot_x.c @@ -127,7 +127,7 @@ #define OPTIBOOT_CUSTOMVER 0 #endif -unsigned const int __attribute__((section(".version"))) +unsigned const int __attribute__((section(".version"))) __attribute__((used)) optiboot_version = 256*(OPTIBOOT_MAJVER + OPTIBOOT_CUSTOMVER) + OPTIBOOT_MINVER; @@ -135,13 +135,13 @@ optiboot_version = 256*(OPTIBOOT_MAJVER + OPTIBOOT_CUSTOMVER) + OPTIBOOT_MINVER; #include FUSES = { -// .WDTCFG, /* Watchdog Configuration */ -// .BODCFG, /* BOD Configuration */ - .OSCCFG = 2, /* Oscillator Configuration */ -// .TCD0CFG, /* TCD0 Configuration */ - .SYSCFG0 = 0xC8, /* RESET is active */ + .WDTCFG = 0, /* Watchdog Configuration */ + .BODCFG = FUSE_BODCFG_DEFAULT, /* BOD Configuration */ + .TCD0CFG = FUSE_TCD0CFG_DEFAULT, /* TCD0 Configuration */ + .OSCCFG = 2, /* 20MHz */ + .SYSCFG0 = 0xC4, /* RESET is not yet */ .SYSCFG1 = 0x06, /* startup 32ms */ -// .APPEND = 0, /* Application Code Section End */ + .APPEND = 0, /* Application Code Section End */ .BOOTEND = 2 /* Boot Section End */ }; @@ -296,8 +296,8 @@ int main (void) { * and still skip bootloader if not necessary */ ch = RSTCTRL.RSTFR; - RSTCTRL.RSTFR = ch; // reset causes, for now. - +// RSTCTRL.RSTFR = ch; // reset causes, for now. + ch &= ~RSTCTRL_UPDIRF_bm; // clear "reset by UPDI." // Skip all logic and run bootloader if cause is cleared (application request) if (ch != 0) { /* @@ -350,8 +350,8 @@ int main (void) { MYUART.CTRLA = 0; // Interrupts: all off MYUART.CTRLB = USART_RXEN_bm | USART_TXEN_bm; - // Set up watchdog to trigger after 8s - watchdogConfig(WDT_PERIOD_8KCLK_gc); + // Set up watchdog to trigger after 1s + watchdogConfig(WDT_PERIOD_1KCLK_gc); #if (LED_START_FLASHES > 0) || defined(LED_DATA_FLASH) || defined(LED_START_ON) /* Set LED pin as output */ @@ -535,6 +535,7 @@ void flash_led (uint8_t count) { return; } } + watchdogReset(); // for breakpointing } #endif @@ -636,6 +637,7 @@ void app() ch = RSTCTRL.RSTFR; RSTCTRL.RSTFR = ch; // reset causes + __asm__ __volatile__ ("jmp 0"); // similar to running off end of memory _PROTECTED_WRITE(RSTCTRL.SWRR, 1); // cause new reset for (long i=0; i < 1000000; i++) { __asm__ __volatile__("wdr"); diff --git a/optiboot/bootloaders/optiboot/pin_defs_x.h b/optiboot/bootloaders/optiboot/pin_defs_x.h index af2cc2e..700a83d 100644 --- a/optiboot/bootloaders/optiboot/pin_defs_x.h +++ b/optiboot/bootloaders/optiboot/pin_defs_x.h @@ -759,10 +759,15 @@ #endif // Tiny402/etc /* - * 14pin Tiny0, Tiny1 + * 14pin and 20pin Tiny0, Tiny1 + * The 14 and 20pin packages both conveniently have the UART on the + * same port pins, and the same pinmux structure! */ -#if defined(__ATtiny1614__) || defined(__ATtiny1604__) || \ - defined(__ATtiny814__) || defined(__ATtiny804__) +#if defined(__AVR_ATtiny1614__) || defined(__AVR_ATtiny1604__) || \ + defined(__AVR_ATtiny814__) || defined(__AVR_ATtiny804__) || \ + defined(__AVR_ATtiny1606__) || defined(__AVR_ATtiny806__) || \ + defined(__AVR_ATtiny406__) || defined(__AVR_ATtiny3216__) || \ + defined(__AVR_ATtiny816__) || defined(__AVR_ATtiny416__) #define MYPMUX PORTMUX.CTRLB # if (UARTTX == B2) # ifndef USART0 @@ -782,10 +787,6 @@ # endif #endif -#if defined(__ATtiny3216__) || defined(__ATtiny1606__) -#endif - - #ifndef MYUART # warning No UARTTX pin specified. #endif