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The RST spec does not appear to believe in intra-cell line continuation as appeared to be expected by the original author. Widen columns and unbreak words to fix output.
96 lines
10 KiB
ReStructuredText
96 lines
10 KiB
ReStructuredText
Exception Causes (EXCCAUSE)
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===========================
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| EXCCAUSE | Cause Name | Cause Description | Required | EXCVADDR |
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| Code | | | Option | Loaded |
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+==========+================================+=========================================+=============+==========+
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| 0 | IllegalInstructionCause | Illegal instruction | Exception | No |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 1 | SyscallCause | SYSCALL instruction | Exception | No |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 2 | InstructionFetchErrorCause | Processor internal physical address or | Exception | Yes |
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| | | data error during instruction fetch | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 3 | LoadStoreErrorCause | Processor internal physical address or | Exception | Yes |
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| | | data error during load or store | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 4 | Level1InterruptCause | Level-1 interrupt as indicated by set | Interrupt | No |
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| | | level-1 bits in the INTERRUPT register | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 5 | AllocaCause | MOVSP instruction, if caller’s | Windowed | No |
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| | | registers are not in the register file | Register | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 6 | IntegerDivideByZeroCause | QUOS, QUOU, REMS, or REMU divisor | 32-bit | No |
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| | | operand is zero | Integer | |
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| | | | Divide | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 7 | Reserved for Tensilica | | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 8 | PrivilegedCause | Attempt to execute a privileged | MMU | No |
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| | | operation when CRING != 0 | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 9 | LoadStoreAlignmentCause | Load or store to an unaligned address | Unaligned | Yes |
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| | | | Exception | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 10..11 | Reserved for Tensilica | | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 12 | InstrPIFDateErrorCause | PIF data error during instruction fetch | Processor | Yes |
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| | | | Interface | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 13 | LoadStorePIFDataErrorCause | Synchronous PIF data error during | Processor | Yes |
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| | | LoadStore access | Interface | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 14 | InstrPIFAddrErrorCause | PIF address error during instruction | Processor | Yes |
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| | | fetch | Interface | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 15 | LoadStorePIFAddrErrorCause | Synchronous PIF address error during | Processor | Yes |
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| | | LoadStore access | Interface | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 16 | InstTLBMissCause | Error during Instruction TLB refill | MMU | Yes |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 17 | InstTLBMultiHitCause | Multiple instruction TLB entries | MMU | Yes |
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| | | matched | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 18 | InstFetchPrivilegeCause | An instruction fetch referenced a | MMU | Yes |
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| | | virtual address at a ring level less | | |
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| | | than CRING | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 19 | Reserved for Tensilica | | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 20 | InstFetchProhibitedCause | An instruction fetch referenced a page | Region | Yes |
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| | | mapped with an attribute that does not | Protection | |
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| | | permit instruction fetch | or MMU | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 21..23 | Reserved for Tensilica | | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 24 | LoadStoreTLBMissCause | Error during TLB refill for a load or | MMU | Yes |
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| | | store | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 25 | LoadStoreTLBMultiHitCause | Multiple TLB entries matched for a load | MMU | Yes |
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| | | or store | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 26 | LoadStorePrivilegeCause | A load or store referenced a virtual | MMU | Yes |
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| | | address at a ring level less than CRING | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 27 | Reserved for Tensilica | | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 28 | LoadProhibitedCause | A load referenced a page mapped with an | Region | Yes |
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| | | attribute that does not permit loads | Protection | |
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| | | | or MMU | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 29 | StoreProhibitedCause | A store referenced a page mapped with | Region | Yes |
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| | | an attribute that does not permit | Protection | |
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| | | | or MMU | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 30..31 | Reserved for Tensilica | | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 32..39 | CoprocessornDisabled | Coprocessor n instruction when cpn | Coprocessor | No |
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| | | disabled. n varies 0..7 as the cause | | |
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| | | varies 32..39 | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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| 40..63 | Reserved | | | |
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+----------+--------------------------------+-----------------------------------------+-------------+----------+
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Infos from Xtensa Instruction Set Architecture (ISA) Reference Manual
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