* PoC cache configuration control
Expaned boards.txt.py to allow new MMU options and create revised .ld's
Updated eboot to pass 48K IRAM segments.
Added Cache_Read_Enable intercept to modify call for 16K ICACHE
Update platform.txt to pass new mmu options through to compiler and linker preprocessor.
Added quick example: esp8266/MMU48K
* Style corrections
Added MMU_ qualifier to new defines.
Moved changes into their own file.
Don't know how to fix platformio issue.
* Added detailed description for Cache_Read_Enable.
Updated tools/sizes.py to report correct IRAM size and indicate ICACHE size.
Merged in earlephilhower's work on unaligned exception. Refactored and added
support for store operations and changed the name to be more closely aligned
with its function. Improved crash reporting path.
* Style and MMU_SEC_HEAP corrections.
* Improved asm register usage.
Added some inline functions to aid in byte and short access to iRAM.
* only byte read has been tested
Updated .ld file to work better with platform.io; however, I am still
missing some steps, so platformio will still fail.
* Interesting glitch in boards.txt after github merge. A new board in
master was missing new additions added by boards.txt.py in the PR.
Which the CI flags when it rebuilds boards.txt.
* Support for 2nd Heap, excess IRAM, through umm_malloc.
Adapted changes to umm_malloc, Esp.cpp, StackThunk.cpp,
WiFiClientSecureBearSSL.cpp, and virtualmem.ino to irammem.ino from
@earlephilhower PR #6994.
Reworked umm_malloc to use context pointers instead of copy context.
umm_malloc now supports allocations from IRAM. Added class
HeapSelectIram, ... to aid in selecting alternate heaps,
modeled after class InterruptLock.
Restrict alloc request from ISRs to DRAM.
Never ending improvements to debug printing.
Sec Heap option now pulls in free IRAM left over in the 1st 32K block.
Managed through umm_malloc with HeapSelectIram.
Updated examples.
* Post push CI cleanup.
* Cleanup part II
* Cleanup part III
* Updates to support platformio, maybe.
* Added exception C wrapper replacement.
* CI Cleanup
* CI Cleanup II
Don't know what to do with platformio it doesn't like my .S file.
ifdef out USE_ISR_SAFE_EXC_WRAPPER to block the new assemlby module
from building on platformio only.
* Changes to exc-c-wrapper-handler.S to assemble under platformio.
* For platformio, Correction to toolchain-xtensa include path.
@mcspr, Thankyou!
* Temporarily added --print-memory-usage to ld parameters for cross-checking IRAM size.
* undo change to platform.txt
* correct merge conflict. take 1
* Fixed #if... for building umm_get_oom_count. It was not building when UMM_STATS_FULL was used.
* Commented out XMC support. Compatibility issues with PoC when using 16K ICACHE.
* Corrected size.py, DRAM bracketing changed to not include ICACHE with DRAM total.
* Added additional _context for support of use of UMM_INLINE_METRICS.
Corrected some UMM_POSION missed edits.
* Changes to clear errors and warnings from toolchain 10.1
Several fixes and improvements to example MMU48K.
With the improved optimization in toolchain 10.1 The example divide by 0
exception was failing with a HWDT event instead of its exception handler.
The compiler saw the obscured divide by 0 and replaced it with a break point.
* Isolated incompatable definitions related to _xtos_set_exception_handler.
GDBSTUB definitions are different from the BootROM's.
* Update tools/platformio-build.py
Co-authored-by: Max Prokhorov <prokhorov.max@outlook.com>
* Requested changes
Changed mmu related usages of ETS_... defines to DBG_MMU_...
Cleanup in example MMU48K.ino. Removed stale memory reference macro
and mmu_status print statement. Cleanup printf '\n' to be '\r\n'.
Improved issolation of development debug prints from the rest of the debug prints.
* Corrected comment. And added missing include.
* Improve comment.
* style and comment correction
* Added draft mmu.rst file and updated index.
Updated example HeapMetric.ino to also illustrate use of IRAM
Improved comments in exc-c-wrapper-handler.S. Added insurance IRQ disable.
* Updated mmu.rst
Improved function name uniqueness for is_iram, is_dram, and is_icache by
adding prefix mmu_. Also, made them available outside of a debug build.
Made pointer precision width more specific.
Made some of the static inline functions in mmu_irm.h safe for ISRs by
setting then for always inline.
* Add a default MMU_IRAM_SIZE value for a new CI test to pass.
Extended use 'umm_heap_context_t *_context' argument in ..._core functions
and expanded its usage to reduce unnecessary repeated calls to
umm_info(NULL, false), also removed recursion from umm_info(NULL, true).
Fixed stack buffer length in umm_info_safe_printf_P and heap.cpp.
Added example for creating an IRAM reserve section.
Updated mmu.rst. Grammar and spelling corrections.
* CI appeasement
* CI appeasement with comment correction.
* Ensure SYS always runs with DRAM Heap selected.
* Add/move heap stack overflow/underflow check to Esp.cpp where the event was discarded.
* Improved comment clarity of purpose for IramReserve.ino. Clean up MMU48K.ino
* Added missing #include
* Corrected usage of warning
* CI appeasement and use #message not #pragma message
* Updated git version of eboot.elf to match build version.
Good test catch.
* Remove conditional build option USE_ISR_SAFE_EXC_WRAPPER, always install.
Use the replacement wrapper on non32xfer_exception_handler install.
Added comments to code describing some exception handling issues.
* Updated mmu.rst
* Expanded and clarified comments.
Limited access to some detailed typdefs/prototypes to .cpp
modules, to avoid future build conflicts.
Completed TODO for verifing that the "C" structure struct __exception_frame
matches the ASM version.
Fixed some typo's, code rot, and added some more cases in examaple irammem.ino.
Refactored a little and reordered printing to ease comparison between methods.
Corrected `#ifdef __cplusplus` coverage area. Cleaned up `extern "C" ...` usage.
Fixes issues with including mmu_iram.h or esp8266_undocumented.h in .c files.
* Style fixes and more cleanup
* Style fix
* Remove unnessasary IRAM_ATTR from install_non32xfer_exception_handler
Some comment tuning.
In the context of _xtos_set_exception_handler and the functions it registers,
changed to type int for exception cause type. This is also the type used by gdbstub
and some other Xtensa files I found.
Recent releases may work better with some newer MacOS releases
according to their commit logs.
Ensure esptool detects the flash size and doesn't use the one hardcoded
in the bootloader. Thanks to @d-a-v for noticing the esptool change.
* every other ci builder uses waveform phase lock
* fix indentation
* same defaults for PIO as in IDE
* CI: force logging without error/warning
* remove forced logging
* Re-implement PWM generator logic
Add special-purpose PWM logic to preserve alignment of PWM signals for
things like RGB LEDs.
Keep a sorted list of GPIO changes in memory. At time 0 of the PWM
cycle, set all pins to high. As time progresses bring down the
additional pins as their duty cycle runs out. This way all PWM signals
are time aligned by construction.
This also reduces the number of PWM interrupts by up to 50%. Before,
both the rising and falling edge of a PWM pin required an interrupt (and
could shift arround accordingly). Now, a single IRQ sets all PWM rising
edges (so 1 no matter how many PWM pins) and individual interrupts
generate the falling edges.
The code favors duty cycle accuracy over PWM period accuracy (since PWM
is simulating an analog voltage it's the %age of time high that's the
critical factor in most apps, not the refresh rate). Measurements give
it about 35% less total error over full range at 20khz than master.
@me-no-dev used something very similar in the original PWM generator.
* Adjust running PWM when analogWriteFreq changed
Use fixed point math to adjust running PWM channels to the new
frequency.
* Also preserve phase of running tone/waveforms
Copy over full high/low periods only on the falling edge of a cycle,
ensuring phase alignment for Tone and Servo.
* Clean up signed/unsigned mismatch, 160MHz operat'n
* Turn off PWM on a Tone or digitalWrite
Ensure both the general purpose waveform generator and the PWM generator
are disabled on a pin used for Tone/digitalWrite.
* Remove hump due to fixed IRQ delta
A hump in the dueling PWMs was very prominent in prior pulls.
The hump was caused by having a PWM falling edge just before the cycle
restart, while having the other channel requesting a 1->0 transition
just outside the busy-loop window of 10us. So it gets an IRQ for channel
B 0->1, then waits 2..8us for the next PWM full cycle 0->1, and ends up
returning from interrupt and not scheduling another IRQ for 10us...hence
the horizontal leg of the bump...
Reduce the minimum IRQ latency a little bit to minimize this effect.
There will still be a (significantly smaller) hump when things cross, but
it won't be anywhere near as bad or detectable.
* Speed PWM generator by reordering data struct
Breaking out bitfields required a load and an AND, slowing things down
in the PWM loop. Convert the bitfield into two separate natural-sized
arrays to reduce code size and increase accuracy.
* Remove if() that could never evaluate TRUE
* Add error feedback to waveform generation
Apply an error term to generated waveform phase times to adjust for any
other ongoing processes/waveforms. Take the actual edge generation
times, subtract them from the desired, and add 1/4 of that (to dampen
any potential oscillations) to the next similar phase of that waveform.
Allows the waveform to seek its proper period and duty cycle without
hardcoding any specific calibrations (which would change depending on
the codepaths, compiler options, etc.) in the source.
* Move _stopPWM and _removePWMEntry to IRAM
Thanks to @dok-net for noticing these need to be in IRAM as they may be
called by digitalWrites in an IRQ.
* Avoid long wait times when PWM freq is low
* Fix bug where tone/pwm could happen on same pin
* Adjust for random 160MHZ operation
The WiFi stack sometimes changes frequency behind our backs, so ESP's
cycle counter does not count constant ticks.
We can't know how long it's been at a different than expected frequency,
so do the next best thing and make sure we adjust any ESP cycles we're
waiting for by the current CPU speed.
This can lead to a blip in the waveform for 1 period when the frequency
toggles from normal, and when it toggles back, but it should remain
for the intervening periods.
Should avoid a lot of LED shimmering and servo errors during WiFi
connection (and maybe transmission).
* Clean up leftover debugs in ISR
* Subtract constant-time overhead for PWM, add 60khz
PWM has a constant minimum time between loops with a single pin, so pull
that time out of the desired PWM period and shift the center of the PWM
frequency closer to the desired without any dynamic feedback needed.
Enable 60khz PWM, even though it's not terribly useful as it causes an
IRQ every ~8us (and each IRQ is 2-3us). The core can still run w/o WDT,
but it's performance is about 5x slower than unloaded.
* Fix GPIO16 not toggling properly.
* Remove constant offset to PWM period
analogWrite doesn't know about the change in total PWM cycles, so it is
possible for it to send in a value that's beyond the maximum adjusted
PWM cycle count, royally messing up things. Remove the offset.
Also, fix bug with timer callback functions potentially disabling the
timer if PWM was still active.
* Remove volatiles, replace with explicit membarrier
Volatiles are expensive in flash/IRAM as well as in runtime because they
introduce `memw` instructions everywhere their values are used.
Remove the volatiles and manually mark handshake signals for
re-read/flush to reduce code and runtime in the waveform generator/PWM.
* Consolidate data into single structure
Save IRAM and flash by using a class to hold waveform generator state.
Allows for bast+offset addressing to be used in many cases, removing
`l32r` and literals from the assembly code.
* Factor out common timer shutdown code
* Remove unneeded extra copy on PWM start
* Factor out common edge work in waveform loop
* Factor out waveform phase feedback loop math
* Reduce PWM size by using 32b count, indexes
Byte-wide operations require extra instructions, so make index and count
a full 32-bits wide.
* GP16O is a 1-bit register, just write to it
Testing indicates that GP16O is just a simple 1-bit wide register in the
RTC module. Instead of |= and &- (i.e. RmW), use direct assignment in
PWM generator.
* Increase PWM linearity in low/high regions
By adjusting the PWM cycle slightly to account for the fixed time
through the compute loop, increase the linear response near the min and
max areas.
* Remove redundant GetCycleCount (non-IRQ)
* Factor out common timer setup operations
* Fix clean-waveform transition, lock to tone faster
New startWaveform waveforms were being copied over on the falling edge
of the cycle, not the rising edge. Everything else is based on rising
edge, so adjust accordingly.
Also, feedback a larger % of the error term in standard waveform
generation. Balances the speed at which it locks to tones under
changing circumstances with it not going completely bonkers when a
transient error occurs due to some other bit.
* Reduce IRAM by pushing more work to _setPWM
Simply mark pins as inactive, don't adjust the ordered list until the
next _startPWM call (in IROM).
* Fix typo in PWM pin 1->0 transition
Actually check the pin mask is active before setting the PWM pin low.
D'oh.
* Combine cleanup and pin remove, save 50 bytes IROM
The cleanup (where marked-off pins are removed from the PWM time map)
and remove (where a chosen pin is taken out of the PWM map) do
essentially the same processing. Combine them and save ~50 bytes of
code and speed things up a tiny bit.
* Remove unused analogMap, toneMap
Save ~100 bytes of IROM by removing the tone/analog pin tracking from
the interface functions. They were completely unused.
* Save IRAM/heap by adjusting WVF update struct
The waveform update structure included 2 32-bit quantities (so, used
8 * 17 = 136 bytes of RAM) for the next cycle of a waveform.
Replace that with a single update register, in a posted fashion. The
logic now sets the new state of a single waveform and returns
immediately (so, no need to wait 1ms if you've got an existing waveform
of 1khz). The waveform NMI will pick up the changed value on its next
cycle.
Reduces IRAM by 40 bytes, and heap by 144 bytes.
* Don't duplicate PWM period calculation
Let the waveform generator be the single source of truth for the PWM
period in clock cycles.
Reduces IRAM by 32 bytes and makes things generally saner.
* Factor out common PWM update code
Replace repeated PWM update logic with a subroutine, and move the
PWMUpdate pointer into the state itself. Reduces IROM and IRAM,
removes code duplication.
Also remove single-use macros and ifdef configurable options as the
IRAM and IROM impact of them are now not very large.
* Fix regression when analogWrite done cold
Lost an `initTimer()` call in a refactoring, resulting in the core
hanging forever while waiting for the NMI which will never happen.
Re-add as appropriate.
* Save 16b of IRAM by not re-setting edge intr bit
Per @dok-net, drop the rewrite of the edge trigger flag in the timer
interrupt register. It's set on startup and never cleared, so this is
redundant. Drops ~16 bytes of IRAM.
* Allow on-the-fly PWM frequency changes
When PWM is running and analogWriteFreq is called, re-calculate the
entire set of PWM pins to the new frequency. Preserve the raw
numerator/denominator in an unused bit of the waveform structure to
avoid wasting memory.
* Adjust for fixed overhead on PWM period
Pulls the actual PWM period closer to the requested one with a simple,
0-overhead static adjustment.
* Fix value reversal when analogWrite out of range
Silly mistake, swapped high and low values when checking analogWrite for
over/under values. Fixed
* Don't optimize the satopWaveform call
Save a few bytes of IRAM by not using -O2 on the stopWaveform call. It
is not a speed-critical function.
* Avoid side effects in addPWMtoList
* Adjust PWM period as fcn of # of PWM pins
Results in much closer PWM frequency range over any number of PWM pins,
while taking 0 add'l overhead in IRAM or in the IRQ.
* Fix occasional Tone artifacts
When _setPWMFreq was called the initial PWM mask was not set to 0
leading to occasional issues where non-PWM pins would be set to 1
on the nextPWM cycle. Manifested itself as an overtone at the PWM
frequency +/-.
* Reduce CPU usage and enhance low range PWM output
Borrow a trick from #7022 to exit the busy loop when the next event is
too far out. Also reduce the IRQ delta subtraction because it was
initially not NMI so there was much more variation than now.
Keep the PWM state machine active at a higher prio than the standard
tone generation when the next edge is very close (i.e. when we're at
the max or min of the range and have 2 or more near edges). Adds a
lot of resolution to the response at low and high ranges.
Go from relative to absolute cycle counts in the main IRQ loop so that
we don't mingle delta-cycles when the delta start was significantly
different.
* Update min IRQ time to remove humps in PWM linearity
Keep PWM error <2.0% on entire range, from 0-100%, and remove the
hump seen in testC by fixing the min IRQ delay setting.
* Remove minor bump at high PWM frequencies
The IRQ lead time was a tiny bit undersized, causing IRQs to come back
too late for about .25us worth of PWM range. Adjust the constant
accordingly
* TZ: help newlib parser
Timezones coded with numeric abbreviations <±nn>±nn<±nn>[±nn][,...] are incorrectly parsed
by newlib's TZ parser.
Replacing <±nn> occurences by UNK allows newlib's TZ parser to nicely interpret all timezones.
Detailed explanation in https://github.com/earlephilhower/newlib-xtensa/issues/12
* Do not write more data than requested on PUYA flashes
* Always align flash reads/writes to 4 bytes
* fixup! Always align flash reads/writes to 4 bytes
This commit simplifies the code a bit and fixes a bug that caused wrong number of bytes to be
written
* fixup! Always align flash reads/writes to 4 bytes
* fixup! Always align flash reads/writes to 4 bytes
* Check for result before additional read/write
* Add overloads for unaligned reads/writes
* fixup! Add overloads for unaligned reads/writes
* fixup! Add overloads for unaligned reads/writes
* fixup! Add overloads for unaligned reads/writes
* fixup! Add overloads for unaligned reads/writes
* fixup! Add overloads for unaligned reads/writes
* fixup! Add overloads for unaligned reads/writes
* fixup! Add overloads for unaligned reads/writes
* Add tests for flashRead/flashWrite
* fixup! Add overloads for unaligned reads/writes
* fixup! Add tests for flashRead/flashWrite
* fixup! Add tests for flashRead/flashWrite
* fixup! Add overloads for unaligned reads/writes
* Clean up minor warnings from LGTM.com
LGTM (Semmie) is a tool, bought by GitHub last year, that conducts basic
linting tasks on code and HTML.
Clean up the warnings identified in the latest report:
https://lgtm.com/projects/g/esp8266/Arduino/?mode=list
No functionality should change, however this may fix some issues with
the perl utilities not exiting properly on a Ctrl-C from the command
line.
* Back out HTML changes and rerun boards.txt.py
The GCC10 PR accidentally reverted to an older BearSSL commit. There should
be no code changes, but to keep everything clean move it back ahead to the
proper commit.
* remove lwip-v1.4 specific code
* ditto
* ditto
* fix ip4_addr definition
* CI: change debug builds to use IPv6, remove regular IPv6 builds
* ditto
* split pio CI in four (because they last twice the time of the other builds)
* remove option from pio
* remove lwIP-1.4 from doc
* restore pio CI splitting
* fix CI debug6 script
* ditto
* Upgrade to GCC 9.1 toolchain
* Rebuilt using pure GNU binutils and GCC
Remove dependencies on earlier forked GNU utilities (gcc-xtensa,
binutils-gdb-xtensa) and just use GCC sources, unmodified (except for
patches in the esp-quick-toolchain directories).
* Rebuild bearssl using new toolchain
* Fix GDBstub linkage options
GDB works with pure GNU GCC and pure GNU binutils now. Still warnings
galore, but tested with the example sketch in the docs.
* Fix digitalRead alias warning
* Remove gdb stub warnings w/a pragma
* Fix deprecated implicit copy ctors in IP code
Fix some warnings present in GCC8/9 in the IPAddress code
In AddressListIterator there was a copy constructor which simply copied
the structure bit-for-bit. That's the default operation, so remove it
to avoid the warning there.
IPAddress, add a default copy constructor since the other copy
constructors are simply parsing from one format into a native ip_addr_t.
@d-a-v, can you give these a look over and see if they're good (since
IP stuff is really your domain).
* Fix AxTLS alias function defs to match real code
* Fix WiFiClientSecure implicit default copy ctor
These both use shared-ptrs to handle refcnts to allocated data, so using
the default copy constructor is fine (and has been in use for a long
time).
* Dummy size for heap to avoid GCC 8/9 warnings
Make GCC think _heap_start is large enough to avoid the basic (and
incorrect) bounds-checking warnings it produces. The size chosen is
arbitrary and does not affect the actual size of the heap in any way.
* Make heap an undefined extend array
Instead of a bogus size, use an indefinite size for the heap to avoid
GCC warnings
* Trivial tab to space fix
* Update SDFat to remove FatFile warnings
* Fix ticker function cast warnings in GCC 9
The callback function is defined to take a (void*) as parameter, but our
templates let users use anything that fits inside sizeof(void*) to be
passed in. Add pragmas to stop GCC warnings about this, since we
already check the size of the type will fit in the allocated space.
* Remove GCC support fcn that's in ROM
Manually delete the divdi3.so from the libgcc.a library by running the
updated EQT's 9.1-post script.
* Make exceptions work again, get std::regex up
Exceptions are broken on all builds (GCC4.8-9.1) due to the removal of
the PROGMEM non-32b read exception handler (added in the unstable
pre3.0.0).
Build the exception code with -mforce-l32 and patch
accordingly to avoid LoadStore errors.
Apply patches to select portions of the regex lib which use _stype_
(which is now in flash).
* Rebuild Bearssl using latest GCC push
* Automate building of BearSSL and LWIP w/new toolchain
* Workaround g++ template section problem for exception strings
G++ seems to throw out the section attributes for templates. This means
that the __EXCSTR(a synonym for "PSTR()") is ignored and exception.what
strings are stored in RODATA, eating up RAM.
Workaround by using the linker to place the strings keying off their name
("*__exception_what__*").
* Rebuild moving exception.what to unique names
Exception.whats are now all in __exception_what__ and can be moved by
the linker to flash. Works aroung G++ issue with segments being lost in
templates.
* Rebuild with new LWIP locking
* Update to latest libs, save iram
Move two GCC FP support routines out of iram since they are in ROM
already, saving some add'l IRAM. Same list as gcc 4.8.
* Update BearSSL to latest release
* Fix umm_perf reference to ROM function
* Fix "reinterpret_case is not a constexpr" error
In GCC 9 (and 8 from what I read on SO), a cast of a const int to a
function pointer (via explicit or implicit reinterpret_cast) is not a
constexpr.
````
/home/earle/Arduino/hardware/esp8266com/esp8266/cores/esp8266/umm_malloc/umm_performance.cpp:45:36: error: a reinterpret_cast is not a constant expression
45 | int constexpr (*_rom_putc1)(int) = (int (*)(int))(void*)0x40001dcc;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
````
Remove the constexpr, potentially increasing heap usage by 4 bytes in
debug mode.
* Update libc.a to latest rev
* Full rebuild of toolchain and libs
* Upgrade to GCC 9.2, released in August 2019
Add builds for all 5 cross-compiles to pass CI
* Move to --std=gnu++14 (C++14 + GNU extensions)
* Fix Ticker merge conflict
* Fix json merge conflict
* One more merge diff fix
* Reapply Ticker.h casting warning fixes for gcc9
* Update with fixes from Sming repo for PSTR and ASM
* Upgrade to -gnu4 toolchain
* Move to gnu5 build with add'l softFP from ROM
* Move add'l softFP from IRAM to flash
Per @mikee47, we miss sone add'l soft-FP routined in the linker which
makes them end up in IRAM. Move them explicitly into flash, like a
couple others we have already done this for.
* Move to std=c++17/c17 in platform, remove abs/round
Move to C++17 and C17 standards on the compiler options.
Remove "register" from core since it is deprecated.
Remove the #define abs() and #define round() which a) overwrote the
C stdlib definitions, poorly, and b) broke the GCC core code which used
"abs" as an internal function name.
Now abs() returns an integer, and not whatever was being absoluted.
fabs() etc. can be used if users need fload/double suport.
round() returns a double now, which is basically what it was returning
in the original case since adding/subtracting by a FP.
* Use std::abs/round to replace the macro definitions
Per discussion w/@devyte, preserve the abs() and round() functionality
via the using statement.
* Remove using std::abs which conflicted with C lib headers
* Add 2nd arg (exception handler) to ets_isr_t
Disassembly of the ROM shows there are 2 params to the ets_isr_t
callback. The first is the arg passed in, the second is a pointer to an
exception frame where you can get info about when the IRQ happened.
* Move the gdbstub example to a subdir
The Arduino IDE and the build CI don't build it without a subdir, so
make one for gdbstub's example so it's visible and tested.
* Fix ets_irq_arratch redefinition and core IRQ handlers
Remove a duplicated, different declaration for ets_irq_attach from
ets_sys.h. It never really even matched the other declaration in the
same header.
Update the core to IRQ handlers to fix the prototype and include the
2nd, unused frame parameter.
* Actually rebuild the libc.a using GCC 9.2
* Fix SPISlave interrupt attach's 2nd parameter
* Rebuild eboot.elf with GCC 9
* Update to latest SoftwareSerial for Delegate fix
* Upgrade to GCC 9.3
* Rebuild all arch toolchains
* Move to GCC 10.1
* Merge master and fix eboot build
GCC10 now uses `-fno-common` so the eboot global variables were being
placed in IRAM. Adjust the makefile and rebuild to fix.
* Built complete toolchain for all archs
* Pull in latest PSTR changes and fix GCC10.1 build
Somehow the prior GCC build's -mforce32 patch wasn't applying correctly,
but I was still able to get a binary. Fixed. Also pulled in latest
PSTR changes in progmem.h
* Update platform.io to platform C/C++ standards
* Use PR's toolchain in platformio build
* Fix several asm warnings in PIO build
* Optional stack smash protection -fstack-protector
Add a menu to enable GCC's built-in stack smash protection. When a
subroutine goes past its end of stack, generate a crashdump on function
exit like:
````
GCC detected stack overrun
Stack corrupted, stack smash detected.
>>>stack>>>
ctx: cont
sp: 3fffff20 end: 3fffffc0 offset: 0000
3fffff20: 40202955 00000001 0000001c 4020287e
3fffff30: feefeffe 000000fd 00000000 00000000
...
<<<stack<<<
````
Disabled by default because there is a small per-function code overhead
(and CPU time if the function is called very frequently and is very
small).
BearSSL and LWIP are not built using stack smash detection, yet.
* Fix duplicated stc=gnu99/c17 in build
* Dump faulting function PC in stack overflow
Report a fake exception to have the exception decoder print the actual
faulting function. This won't tell you where in the function the issue
happened, but it will tell you the function name first and foremost.
* Rebuild with Platform.io JSON tag in release tgzs
* Deprecate SPIFFS, move examples to LittleFS
SPIFFS has been a great filesystem, but it has significant problems in
many cases (and it's also pretty slow). Development seems to have
slowed/stopped on the upstream version, and we're not able to provide
support or fix the known issues with it as-is.
Deprecate SPIFFS variable.
Update all examples to use LittleFS instead of SPIFFS.
Also, minor cleanup on very old examples which has obsolete delays
waiting for the Serial port to come up, or which were stuck at 9600 baud
because of their ancient AVR heritage.
Fixes#7095
* Remove leftover debug code
* Clean up comments in some examples
* Update documentation on SPIFFS deprecation
* Fix host tests to avoid deprecation warnings
* Fix cut-n-paste error
* Restore SpeedTest.ino, adjust to allow custom FSes
Co-authored-by: Develo <deveyes@gmail.com>
The OTA script was not reporting the actual reported upload status from
the ESP8266, and instead always printed "Result: OK" no matter what
happened.
Now check for ERROR or OK in final message (and ensure the message is
not accidentally merged with the final byte count) and report properly.
Fixes#7162
* upstream lwIP is now downloaded by a makefile, not subsubmoduled
* lwip2: upstream lwIP not sub-sub-modules anymore
lwip2: Allow IPv4 and IPv6 DNS and SNTP server configured via DHCP to co-exist (patch against upstream)
* lwip2: enable tcp-listen-with-backlog feature
* lwip2 submodule update:
- enable more efficient chksum algorithm thanks to Richard Allen
- enable tcp listener with backlog
* more comments, fix backlog management, fix API
* move default value definition in .cpp
because one must not believe it can be redefined before including WiFiServer.h
* improved backlog handling, it is no more a breaking change
as proposed by https://github.com/esp8266/Arduino/pull/6972#issue-358508056.
@ttytyper 's changes have been incorporate into this PR
The build flag ARDUINO_SONOFF_... should now appear as ARDUINO_ESP8266_SONOFF_...
@ttytyper, @mcspr, and @d-a-v thanks!
* Use a python3 script to call python3
It's odd, but because Windows requires a full Python3 install we must
have an executable called "tools/python3/python3" to use Python3 in the
toolchain.
Before, we simply symlinked to /usr/bin/python3 (for Linux) or
/usr/local/bin/python3 (Mac). Unfortunately, depending on the method of
installation, on MacOS the Python3 executable can be in /usr/bin/python3
instead.
To avoid the entire issue, unify the Mac and Linux python3 placeholders
to use python3 itself to jump to the real executable.
Fixes#6931
* Explicitly remove old symlink to python3
The tar extraction for the updated python3 tarball will fail on systems
that already have a symlink in /tools/python3/python3 because the tar
extractor attempts to open the *target of the symlink* (i.e. the actual
interpreter in /usr/bin or /usr/local/bin).
Add a commented hack to destroy this symlink before expanding the
tarballs, if the file exists. This is safe to do since it will be
overwritten by any extractions of the python3 tarball later in the
process.
Co-authored-by: david gauchard <gauchard@laas.fr>
Only minor updates to headers and no functionality change on the
portions that we use in the ESP8266.
@Teddyz reported random crashes while running against a local MQTT
server and was able to report stack usages of up to 6136 bytes.
Increase the SSL stack to a little more than that, once again.
* Add a CRC32 over progmem and ESP.checkFlashCRC
Automatically embed a CRC32 of the program memory (including bootloader
but excluding any filesystems) in all images in unused space in the
bootloader block.
Add a call, ESP.checkFlashCRC() which returns false if the calculated
CRC doesn't match the one stored in the image (i.e. flash corruption).
Fixes#4165
* Add example that corrupts itself, comments
Show CRC checking catch a 1-bit error in program code by corrupting a
large array, and then return it to clean and verify the CRC matches once
again.
Add comments to the CRC check routine
Clean up pylint complaints on crc32bin.py
* Check linker script for CRC space in bootsector
Add an assertion in the eboot linker file to guarantee that we have at
least 8 bytes of unused space at the end of the boot sector to patch in
the CRC. If not, the eboot link will fail.
* Add note about what to do if CRC check fails
Per discussion with @d-a-v.
When the CRC check fails, you could *try* to do certain things (but may
not succeed since there is known flash corruption at that point). List
a few ideas for application authors.
* Only single, flash/ram friendly crc32() function
* Combine the CRC calc and bin generation in 1 step
Per discussion w/@mcspr, combine the CRC calculation with the binary
generation, removing the additional build step.
* Allow GZIP compressed flash updates
Modified the bootloader to be able to take stored updates in compressed
GZIP format (i.e. the output of "gzip -9 xxx.bin") and decompress them
on-the-fly to their final destination. This can work for apps and for
filesystems (when used with the 2-step update option).
Allow eboot to be built using -Os/2 optimizations by fixing some portions
which failed when any optimizations were used. Add -Wall and use data
and function sections to reduce size. Use -Os to minimize size.
Remove obsolete esptool-ck calls to build a .ROM image, we don't use it.
Move all uninitted variables to RAM from IRAM, allowing 8-bit access.
Hook in @d-a-v and @pfalcon's uzlib port to actually do the
decompression. Do not use any CRC checking which saves space. Since we
have overwritten all of flash by the time we know id the CRC matches,
there's nothing we could have done anyway.
Adjust the Updater class to support GZIP files and not attempt to patch
them.
Bootloader builds to 0xd90 out of 0xfff bytes.
* Add @d-a-v's patch for httpupdate
https://github.com/esp8266/Arduino/pull/6820#pullrequestreview-326541014
* Update uzlib to point to pfalcon++
For now, because there are some self-test failures with @d-a-v's esp8266
branch (whose cool new features we don't actually use in eboot now)
start with pfalcon's 2.9 release and add the 2 patches (clcidx to code
from IRAM/RODATA, and the Windows test file renaming) needed to build
and run successfully.
* Add (c) notice for uzlib to README
