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Resolve HWDT Reset with core_esp8266_vm (#9025)

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* Resolve HWDT Reset with core_esp8266_vm

With the newer GCC compiler (after tag 3.0.2), example virtualmem was crashing with a HWDT reset.
Reordered some SPI register set lines in spi_init().
New ordering was based on ::begin in SPI.cpp

This change may resolve issues describe in
https://github.com/esp8266/Arduino/discussions/9010

* Added memory barrier to changes
spi_ctrl appears to need setting before other SPI registers
This commit is contained in:
M Hightower 2023-11-12 17:26:35 -05:00 committed by GitHub
parent 7fc2caa72f
commit c84fda145c
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1 changed files with 4 additions and 3 deletions
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7
cores/esp8266/core_esp8266_vm.cpp
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@ -161,20 +161,21 @@ static struct cache_line *__vm_cache; // Always points to MRU (hence the line be
constexpr int addrmask = ~(sizeof(__vm_cache[0].w)-1); // Helper to mask off bits present in cache entry
static void spi_init(spi_regs *spi1)
{
pinMode(sck, SPECIAL);
pinMode(miso, SPECIAL);
pinMode(mosi, SPECIAL);
pinMode(cs, SPECIAL);
spi1->spi_cmd = 0;
// spi_ctrl appears to need setting before other SPI registers
spi1->spi_ctrl = 0; // MSB first + plain SPI mode
asm("" ::: "memory");
GPMUX &= ~(1 << 9);
spi1->spi_clock = spi_clkval;
spi1->spi_ctrl = 0 ; // MSB first + plain SPI mode
spi1->spi_ctrl1 = 0; // undocumented, clear for safety?
spi1->spi_ctrl2 = 0; // No add'l delays on signals
spi1->spi_user2 = 0; // No insn or insn_bits to set
spi1->spi_cmd = 0;
}
// Note: GCC optimization -O2 and -O3 tried and returned *slower* code than the default