From c84fda145c4f836603f8a1837854915fc52693d9 Mon Sep 17 00:00:00 2001
From: M Hightower <27247790+mhightower83@users.noreply.github.com>
Date: Sun, 12 Nov 2023 17:26:35 -0500
Subject: [PATCH] Resolve HWDT Reset with core_esp8266_vm (#9025)

* Resolve HWDT Reset with core_esp8266_vm

With the newer GCC compiler (after tag 3.0.2), example virtualmem was crashing with a HWDT reset.
Reordered some SPI register set lines in spi_init().
New ordering was based on ::begin in SPI.cpp

This change may resolve issues describe in
https://github.com/esp8266/Arduino/discussions/9010

* Added memory barrier to changes
spi_ctrl appears to need setting before other SPI registers
---
 cores/esp8266/core_esp8266_vm.cpp | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/cores/esp8266/core_esp8266_vm.cpp b/cores/esp8266/core_esp8266_vm.cpp
index 3a63d65f7..00f50e398 100644
--- a/cores/esp8266/core_esp8266_vm.cpp
+++ b/cores/esp8266/core_esp8266_vm.cpp
@@ -161,20 +161,21 @@ static struct cache_line *__vm_cache; // Always points to MRU (hence the line be
 
 constexpr int addrmask = ~(sizeof(__vm_cache[0].w)-1); // Helper to mask off bits present in cache entry
 
-
 static void spi_init(spi_regs *spi1)
 {
   pinMode(sck, SPECIAL);
   pinMode(miso, SPECIAL);
   pinMode(mosi, SPECIAL);
   pinMode(cs, SPECIAL);
-  spi1->spi_cmd = 0;
+  // spi_ctrl appears to need setting before other SPI registers
+  spi1->spi_ctrl = 0;  // MSB first + plain SPI mode
+  asm("" ::: "memory");
   GPMUX &= ~(1 << 9);
   spi1->spi_clock = spi_clkval;
-  spi1->spi_ctrl = 0 ; // MSB first + plain SPI mode
   spi1->spi_ctrl1 = 0; // undocumented, clear for safety?
   spi1->spi_ctrl2 = 0; // No add'l delays on signals
   spi1->spi_user2 = 0; // No insn or insn_bits to set
+  spi1->spi_cmd = 0;
 }
 
 // Note: GCC optimization -O2 and -O3 tried and returned *slower* code than the default