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[sam] committing state-of-the-art code: compiling under EWARM 6.21.1 but debug not easy

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This commit is contained in:
Thibaut VIARD
2011-09-05 22:59:49 +02:00
parent bb4c1af790
commit 8f01f92e87
463 changed files with 89903 additions and 0 deletions
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29
hardware/sam/system/libsam/cmsis/sam3u/include/instance/adc.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_ADC_INSTANCE_
#define _SAM3U_ADC_INSTANCE_
/* ========== Register definition for ADC peripheral ========== */
#define REG_ADC_CR REG_ACCESS(WoReg, 0x400AC000U) /**< \brief (ADC) Control Register */
#define REG_ADC_MR REG_ACCESS(RwReg, 0x400AC004U) /**< \brief (ADC) Mode Register */
#define REG_ADC_CHER REG_ACCESS(WoReg, 0x400AC010U) /**< \brief (ADC) Channel Enable Register */
#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x400AC014U) /**< \brief (ADC) Channel Disable Register */
#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x400AC018U) /**< \brief (ADC) Channel Status Register */
#define REG_ADC_SR REG_ACCESS(RoReg, 0x400AC01CU) /**< \brief (ADC) Status Register */
#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
#define REG_ADC_IER REG_ACCESS(WoReg, 0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
#define REG_ADC_IDR REG_ACCESS(WoReg, 0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
#define REG_ADC_IMR REG_ACCESS(RoReg, 0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
#define REG_ADC_CDR REG_ACCESS(RoReg, 0x400AC030U) /**< \brief (ADC) Channel Data Register */
#define REG_ADC_RPR REG_ACCESS(RwReg, 0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
#define REG_ADC_RCR REG_ACCESS(RwReg, 0x400AC104U) /**< \brief (ADC) Receive Counter Register */
#define REG_ADC_TPR REG_ACCESS(RwReg, 0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */
#define REG_ADC_TCR REG_ACCESS(RwReg, 0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */
#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */
#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */
#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x400AC120U) /**< \brief (ADC) Transfer Control Register */
#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x400AC124U) /**< \brief (ADC) Transfer Status Register */
#endif /* _SAM3U_ADC_INSTANCE_ */

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hardware/sam/system/libsam/cmsis/sam3u/include/instance/adc12b.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_ADC12B_INSTANCE_
#define _SAM3U_ADC12B_INSTANCE_
/* ========== Register definition for ADC12B peripheral ========== */
#define REG_ADC12B_CR REG_ACCESS(WoReg, 0x400A8000U) /**< \brief (ADC12B) Control Register */
#define REG_ADC12B_MR REG_ACCESS(RwReg, 0x400A8004U) /**< \brief (ADC12B) Mode Register */
#define REG_ADC12B_CHER REG_ACCESS(WoReg, 0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */
#define REG_ADC12B_CHDR REG_ACCESS(WoReg, 0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */
#define REG_ADC12B_CHSR REG_ACCESS(RoReg, 0x400A8018U) /**< \brief (ADC12B) Channel Status Register */
#define REG_ADC12B_SR REG_ACCESS(RoReg, 0x400A801CU) /**< \brief (ADC12B) Status Register */
#define REG_ADC12B_LCDR REG_ACCESS(RoReg, 0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */
#define REG_ADC12B_IER REG_ACCESS(WoReg, 0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */
#define REG_ADC12B_IDR REG_ACCESS(WoReg, 0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */
#define REG_ADC12B_IMR REG_ACCESS(RoReg, 0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */
#define REG_ADC12B_CDR REG_ACCESS(RoReg, 0x400A8030U) /**< \brief (ADC12B) Channel Data Register */
#define REG_ADC12B_ACR REG_ACCESS(RwReg, 0x400A8064U) /**< \brief (ADC12B) Analog Control Register */
#define REG_ADC12B_EMR REG_ACCESS(RwReg, 0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */
#define REG_ADC12B_RPR REG_ACCESS(RwReg, 0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */
#define REG_ADC12B_RCR REG_ACCESS(RwReg, 0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */
#define REG_ADC12B_TPR REG_ACCESS(RwReg, 0x400A8108U) /**< \brief (ADC12B) Transmit Pointer Register */
#define REG_ADC12B_TCR REG_ACCESS(RwReg, 0x400A810CU) /**< \brief (ADC12B) Transmit Counter Register */
#define REG_ADC12B_RNPR REG_ACCESS(RwReg, 0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */
#define REG_ADC12B_RNCR REG_ACCESS(RwReg, 0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */
#define REG_ADC12B_TNPR REG_ACCESS(RwReg, 0x400A8118U) /**< \brief (ADC12B) Transmit Next Pointer Register */
#define REG_ADC12B_TNCR REG_ACCESS(RwReg, 0x400A811CU) /**< \brief (ADC12B) Transmit Next Counter Register */
#define REG_ADC12B_PTCR REG_ACCESS(WoReg, 0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */
#define REG_ADC12B_PTSR REG_ACCESS(RoReg, 0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */
#endif /* _SAM3U_ADC12B_INSTANCE_ */

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hardware/sam/system/libsam/cmsis/sam3u/include/instance/chipid.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_CHIPID_INSTANCE_
#define _SAM3U_CHIPID_INSTANCE_
/* ========== Register definition for CHIPID peripheral ========== */
#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
#endif /* _SAM3U_CHIPID_INSTANCE_ */

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hardware/sam/system/libsam/cmsis/sam3u/include/instance/dmac.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_DMAC_INSTANCE_
#define _SAM3U_DMAC_INSTANCE_
/* ========== Register definition for DMAC peripheral ========== */
#define REG_DMAC_GCFG REG_ACCESS(RwReg, 0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
#define REG_DMAC_EN REG_ACCESS(RwReg, 0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
#define REG_DMAC_SREQ REG_ACCESS(RwReg, 0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
#define REG_DMAC_CREQ REG_ACCESS(RwReg, 0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
#define REG_DMAC_LAST REG_ACCESS(RwReg, 0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
#define REG_DMAC_SYNC REG_ACCESS(RwReg, 0x400B0014U) /**< \brief (DMAC) DMAC Request Synchronization Register */
#define REG_DMAC_EBCIER REG_ACCESS(WoReg, 0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
#define REG_DMAC_EBCIDR REG_ACCESS(WoReg, 0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
#define REG_DMAC_EBCIMR REG_ACCESS(RoReg, 0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
#define REG_DMAC_EBCISR REG_ACCESS(RoReg, 0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */
#define REG_DMAC_CHER REG_ACCESS(WoReg, 0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
#define REG_DMAC_CHDR REG_ACCESS(WoReg, 0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
#define REG_DMAC_CHSR REG_ACCESS(RoReg, 0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
#define REG_DMAC_SADDR0 REG_ACCESS(RwReg, 0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
#define REG_DMAC_DADDR0 REG_ACCESS(RwReg, 0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
#define REG_DMAC_DSCR0 REG_ACCESS(RwReg, 0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
#define REG_DMAC_CTRLA0 REG_ACCESS(RwReg, 0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
#define REG_DMAC_CTRLB0 REG_ACCESS(RwReg, 0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
#define REG_DMAC_CFG0 REG_ACCESS(RwReg, 0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
#define REG_DMAC_SPIP0 REG_ACCESS(RwReg, 0x400B0054U) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 0) */
#define REG_DMAC_DPIP0 REG_ACCESS(RwReg, 0x400B0058U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 0) */
#define REG_DMAC_SADDR1 REG_ACCESS(RwReg, 0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
#define REG_DMAC_DADDR1 REG_ACCESS(RwReg, 0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
#define REG_DMAC_DSCR1 REG_ACCESS(RwReg, 0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
#define REG_DMAC_CTRLA1 REG_ACCESS(RwReg, 0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
#define REG_DMAC_CTRLB1 REG_ACCESS(RwReg, 0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
#define REG_DMAC_CFG1 REG_ACCESS(RwReg, 0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
#define REG_DMAC_SPIP1 REG_ACCESS(RwReg, 0x400B007CU) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 1) */
#define REG_DMAC_DPIP1 REG_ACCESS(RwReg, 0x400B0080U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 1) */
#define REG_DMAC_SADDR2 REG_ACCESS(RwReg, 0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
#define REG_DMAC_DADDR2 REG_ACCESS(RwReg, 0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
#define REG_DMAC_DSCR2 REG_ACCESS(RwReg, 0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
#define REG_DMAC_CTRLA2 REG_ACCESS(RwReg, 0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
#define REG_DMAC_CTRLB2 REG_ACCESS(RwReg, 0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
#define REG_DMAC_CFG2 REG_ACCESS(RwReg, 0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
#define REG_DMAC_SPIP2 REG_ACCESS(RwReg, 0x400B00A4U) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 2) */
#define REG_DMAC_DPIP2 REG_ACCESS(RwReg, 0x400B00A8U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 2) */
#define REG_DMAC_SADDR3 REG_ACCESS(RwReg, 0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
#define REG_DMAC_DADDR3 REG_ACCESS(RwReg, 0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
#define REG_DMAC_DSCR3 REG_ACCESS(RwReg, 0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
#define REG_DMAC_CTRLA3 REG_ACCESS(RwReg, 0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
#define REG_DMAC_CTRLB3 REG_ACCESS(RwReg, 0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
#define REG_DMAC_CFG3 REG_ACCESS(RwReg, 0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
#define REG_DMAC_SPIP3 REG_ACCESS(RwReg, 0x400B00CCU) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 3) */
#define REG_DMAC_DPIP3 REG_ACCESS(RwReg, 0x400B00D0U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 3) */
#endif /* _SAM3U_DMAC_INSTANCE_ */

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hardware/sam/system/libsam/cmsis/sam3u/include/instance/efc0.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_EFC0_INSTANCE_
#define _SAM3U_EFC0_INSTANCE_
/* ========== Register definition for EFC0 peripheral ========== */
#define REG_EFC0_FMR REG_ACCESS(RwReg, 0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */
#define REG_EFC0_FCR REG_ACCESS(WoReg, 0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */
#define REG_EFC0_FSR REG_ACCESS(RoReg, 0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */
#define REG_EFC0_FRR REG_ACCESS(RoReg, 0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */
#endif /* _SAM3U_EFC0_INSTANCE_ */

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hardware/sam/system/libsam/cmsis/sam3u/include/instance/efc1.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_EFC1_INSTANCE_
#define _SAM3U_EFC1_INSTANCE_
/* ========== Register definition for EFC1 peripheral ========== */
#define REG_EFC1_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */
#define REG_EFC1_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */
#define REG_EFC1_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */
#define REG_EFC1_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */
#endif /* _SAM3U_EFC1_INSTANCE_ */

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hardware/sam/system/libsam/cmsis/sam3u/include/instance/gpbr.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_GPBR_INSTANCE_
#define _SAM3U_GPBR_INSTANCE_
/* ========== Register definition for GPBR peripheral ========== */
#define REG_GPBR_GPBR REG_ACCESS(RwReg, 0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register */
#endif /* _SAM3U_GPBR_INSTANCE_ */

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hardware/sam/system/libsam/cmsis/sam3u/include/instance/hsmci.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_HSMCI_INSTANCE_
#define _SAM3U_HSMCI_INSTANCE_
/* ========== Register definition for HSMCI peripheral ========== */
#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */
#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */
#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */
#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */
#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */
#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */
#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */
#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */
#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
#define REG_HSMCI_DMA REG_ACCESS(RwReg, 0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */
#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
#define REG_HSMCI_FIFO REG_ACCESS(RwReg, 0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
#endif /* _SAM3U_HSMCI_INSTANCE_ */

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hardware/sam/system/libsam/cmsis/sam3u/include/instance/matrix.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_MATRIX_INSTANCE_
#define _SAM3U_MATRIX_INSTANCE_
/* ========== Register definition for MATRIX peripheral ========== */
#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
#define REG_MATRIX_PRAS5 REG_ACCESS(RwReg, 0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
#define REG_MATRIX_PRAS6 REG_ACCESS(RwReg, 0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
#define REG_MATRIX_PRAS7 REG_ACCESS(RwReg, 0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
#define REG_MATRIX_PRAS8 REG_ACCESS(RwReg, 0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
#define REG_MATRIX_PRAS9 REG_ACCESS(RwReg, 0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
#define REG_MATRIX_MRCR REG_ACCESS(RwReg, 0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
#endif /* _SAM3U_MATRIX_INSTANCE_ */

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hardware/sam/system/libsam/cmsis/sam3u/include/instance/pioa.h Normal file
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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_PIOA_INSTANCE_
#define _SAM3U_PIOA_INSTANCE_
/* ========== Register definition for PIOA peripheral ========== */
#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */
#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */
#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0C08U) /**< \brief (PIOA) PIO Status Register */
#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0C10U) /**< \brief (PIOA) Output Enable Register */
#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0C14U) /**< \brief (PIOA) Output Disable Register */
#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0C18U) /**< \brief (PIOA) Output Status Register */
#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */
#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */
#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */
#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */
#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */
#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */
#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */
#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */
#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */
#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */
#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */
#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */
#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */
#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */
#define REG_PIOA_ABSR REG_ACCESS(RwReg, 0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */
#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */
#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */
#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */
#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */
#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0CC4U) /**< \brief (PIOA) Level Select Register */
#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */
#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0CE0U) /**< \brief (PIOA) Lock Status */
#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */
#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */
#endif /* _SAM3U_PIOA_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_PIOB_INSTANCE_
#define _SAM3U_PIOB_INSTANCE_
/* ========== Register definition for PIOB peripheral ========== */
#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */
#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */
#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOB) PIO Status Register */
#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOB) Output Enable Register */
#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOB) Output Disable Register */
#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOB) Output Status Register */
#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */
#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */
#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */
#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */
#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */
#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */
#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */
#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */
#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */
#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */
#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */
#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */
#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */
#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */
#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */
#define REG_PIOB_ABSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */
#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */
#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */
#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */
#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */
#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOB) Level Select Register */
#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */
#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOB) Lock Status */
#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */
#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */
#endif /* _SAM3U_PIOB_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_PIOC_INSTANCE_
#define _SAM3U_PIOC_INSTANCE_
/* ========== Register definition for PIOC peripheral ========== */
#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOC) PIO Status Register */
#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOC) Output Enable Register */
#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOC) Output Disable Register */
#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOC) Output Status Register */
#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
#define REG_PIOC_ABSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOC) Level Select Register */
#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOC) Lock Status */
#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
#endif /* _SAM3U_PIOC_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_PMC_INSTANCE_
#define _SAM3U_PMC_INSTANCE_
/* ========== Register definition for PMC peripheral ========== */
#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */
#define REG_PMC_PCER REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */
#define REG_PMC_PCDR REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */
#define REG_PMC_PCSR REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */
#define REG_CKGR_UCKR REG_ACCESS(RwReg, 0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
#define REG_CKGR_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
#define REG_CKGR_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
#define REG_CKGR_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */
#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */
#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */
#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
#endif /* _SAM3U_PMC_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_PWM_INSTANCE_
#define _SAM3U_PWM_INSTANCE_
/* ========== Register definition for PWM peripheral ========== */
#define REG_PWM_CLK REG_ACCESS(RwReg, 0x4008C000U) /**< \brief (PWM) PWM Clock Register */
#define REG_PWM_ENA REG_ACCESS(WoReg, 0x4008C004U) /**< \brief (PWM) PWM Enable Register */
#define REG_PWM_DIS REG_ACCESS(WoReg, 0x4008C008U) /**< \brief (PWM) PWM Disable Register */
#define REG_PWM_SR REG_ACCESS(RoReg, 0x4008C00CU) /**< \brief (PWM) PWM Status Register */
#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
#define REG_PWM_SCM REG_ACCESS(RwReg, 0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
#define REG_PWM_OOV REG_ACCESS(RwReg, 0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */
#define REG_PWM_OS REG_ACCESS(RwReg, 0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */
#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
#define REG_PWM_OSC REG_ACCESS(WoReg, 0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */
#define REG_PWM_FSR REG_ACCESS(RoReg, 0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */
#define REG_PWM_FCR REG_ACCESS(WoReg, 0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */
#define REG_PWM_FPV REG_ACCESS(RwReg, 0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */
#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
#define REG_PWM_ELMR REG_ACCESS(RwReg, 0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
#define REG_PWM_RPR REG_ACCESS(RwReg, 0x4008C100U) /**< \brief (PWM) Receive Pointer Register */
#define REG_PWM_RCR REG_ACCESS(RwReg, 0x4008C104U) /**< \brief (PWM) Receive Counter Register */
#define REG_PWM_TPR REG_ACCESS(RwReg, 0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */
#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */
#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x4008C110U) /**< \brief (PWM) Receive Next Pointer Register */
#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x4008C114U) /**< \brief (PWM) Receive Next Counter Register */
#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */
#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */
#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x4008C120U) /**< \brief (PWM) Transfer Control Register */
#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x4008C124U) /**< \brief (PWM) Transfer Status Register */
#define REG_PWM_CMPV0 REG_ACCESS(RwReg, 0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
#define REG_PWM_CMPVUPD0 REG_ACCESS(WoReg, 0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
#define REG_PWM_CMPM0 REG_ACCESS(RwReg, 0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
#define REG_PWM_CMPMUPD0 REG_ACCESS(WoReg, 0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
#define REG_PWM_CMPV1 REG_ACCESS(RwReg, 0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
#define REG_PWM_CMPVUPD1 REG_ACCESS(WoReg, 0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
#define REG_PWM_CMPM1 REG_ACCESS(RwReg, 0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
#define REG_PWM_CMPMUPD1 REG_ACCESS(WoReg, 0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
#define REG_PWM_CMPV2 REG_ACCESS(RwReg, 0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
#define REG_PWM_CMPVUPD2 REG_ACCESS(WoReg, 0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
#define REG_PWM_CMPM2 REG_ACCESS(RwReg, 0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
#define REG_PWM_CMPMUPD2 REG_ACCESS(WoReg, 0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
#define REG_PWM_CMPV3 REG_ACCESS(RwReg, 0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
#define REG_PWM_CMPVUPD3 REG_ACCESS(WoReg, 0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
#define REG_PWM_CMPM3 REG_ACCESS(RwReg, 0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
#define REG_PWM_CMPMUPD3 REG_ACCESS(WoReg, 0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
#define REG_PWM_CMPV4 REG_ACCESS(RwReg, 0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
#define REG_PWM_CMPVUPD4 REG_ACCESS(WoReg, 0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
#define REG_PWM_CMPM4 REG_ACCESS(RwReg, 0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
#define REG_PWM_CMPMUPD4 REG_ACCESS(WoReg, 0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
#define REG_PWM_CMPV5 REG_ACCESS(RwReg, 0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
#define REG_PWM_CMPVUPD5 REG_ACCESS(WoReg, 0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
#define REG_PWM_CMPM5 REG_ACCESS(RwReg, 0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
#define REG_PWM_CMPMUPD5 REG_ACCESS(WoReg, 0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
#define REG_PWM_CMPV6 REG_ACCESS(RwReg, 0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
#define REG_PWM_CMPVUPD6 REG_ACCESS(WoReg, 0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
#define REG_PWM_CMPM6 REG_ACCESS(RwReg, 0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
#define REG_PWM_CMPMUPD6 REG_ACCESS(WoReg, 0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
#define REG_PWM_CMPV7 REG_ACCESS(RwReg, 0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
#define REG_PWM_CMPVUPD7 REG_ACCESS(WoReg, 0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
#define REG_PWM_CMPM7 REG_ACCESS(RwReg, 0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
#define REG_PWM_CMPMUPD7 REG_ACCESS(WoReg, 0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
#endif /* _SAM3U_PWM_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_RSTC_INSTANCE_
#define _SAM3U_RSTC_INSTANCE_
/* ========== Register definition for RSTC peripheral ========== */
#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (RSTC) Control Register */
#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1204U) /**< \brief (RSTC) Status Register */
#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1208U) /**< \brief (RSTC) Mode Register */
#endif /* _SAM3U_RSTC_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_RTC_INSTANCE_
#define _SAM3U_RTC_INSTANCE_
/* ========== Register definition for RTC peripheral ========== */
#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1260U) /**< \brief (RTC) Control Register */
#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1264U) /**< \brief (RTC) Mode Register */
#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1268U) /**< \brief (RTC) Time Register */
#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E126CU) /**< \brief (RTC) Calendar Register */
#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (RTC) Time Alarm Register */
#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1278U) /**< \brief (RTC) Status Register */
#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E128CU) /**< \brief (RTC) Valid Entry Register */
#define REG_RTC_WPMR REG_ACCESS(RwReg, 0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */
#endif /* _SAM3U_RTC_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_RTT_INSTANCE_
#define _SAM3U_RTT_INSTANCE_
/* ========== Register definition for RTT peripheral ========== */
#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1230U) /**< \brief (RTT) Mode Register */
#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1234U) /**< \brief (RTT) Alarm Register */
#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1238U) /**< \brief (RTT) Value Register */
#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (RTT) Status Register */
#endif /* _SAM3U_RTT_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_SMC_INSTANCE_
#define _SAM3U_SMC_INSTANCE_
/* ========== Register definition for SMC peripheral ========== */
#define REG_SMC_CFG REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
#define REG_SMC_CTRL REG_ACCESS(WoReg, 0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
#define REG_SMC_SR REG_ACCESS(RoReg, 0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
#define REG_SMC_IER REG_ACCESS(WoReg, 0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
#define REG_SMC_IDR REG_ACCESS(WoReg, 0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
#define REG_SMC_IMR REG_ACCESS(RoReg, 0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
#define REG_SMC_ADDR REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
#define REG_SMC_BANK REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
#define REG_SMC_ECC_CTRL REG_ACCESS(WoReg, 0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
#define REG_SMC_ECC_MD REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
#define REG_SMC_ECC_SR1 REG_ACCESS(RoReg, 0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
#define REG_SMC_ECC_PR0 REG_ACCESS(RoReg, 0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
#define REG_SMC_ECC_PR1 REG_ACCESS(RoReg, 0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
#define REG_SMC_ECC_SR2 REG_ACCESS(RoReg, 0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
#define REG_SMC_ECC_PR2 REG_ACCESS(RoReg, 0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
#define REG_SMC_ECC_PR3 REG_ACCESS(RoReg, 0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
#define REG_SMC_ECC_PR4 REG_ACCESS(RoReg, 0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
#define REG_SMC_ECC_PR5 REG_ACCESS(RoReg, 0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
#define REG_SMC_ECC_PR6 REG_ACCESS(RoReg, 0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
#define REG_SMC_ECC_PR7 REG_ACCESS(RoReg, 0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
#define REG_SMC_ECC_PR8 REG_ACCESS(RoReg, 0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
#define REG_SMC_ECC_PR9 REG_ACCESS(RoReg, 0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
#define REG_SMC_ECC_PR10 REG_ACCESS(RoReg, 0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
#define REG_SMC_ECC_PR11 REG_ACCESS(RoReg, 0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
#define REG_SMC_ECC_PR12 REG_ACCESS(RoReg, 0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
#define REG_SMC_ECC_PR13 REG_ACCESS(RoReg, 0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
#define REG_SMC_ECC_PR14 REG_ACCESS(RoReg, 0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
#define REG_SMC_ECC_PR15 REG_ACCESS(RoReg, 0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
#define REG_SMC_TIMINGS0 REG_ACCESS(RwReg, 0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
#define REG_SMC_TIMINGS1 REG_ACCESS(RwReg, 0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
#define REG_SMC_TIMINGS2 REG_ACCESS(RwReg, 0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
#define REG_SMC_TIMINGS3 REG_ACCESS(RwReg, 0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
#define REG_SMC_WPCR REG_ACCESS(WoReg, 0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
#endif /* _SAM3U_SMC_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_SPI_INSTANCE_
#define _SAM3U_SPI_INSTANCE_
/* ========== Register definition for SPI peripheral ========== */
#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */
#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */
#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */
#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */
#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */
#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */
#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
#endif /* _SAM3U_SPI_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_SSC_INSTANCE_
#define _SAM3U_SSC_INSTANCE_
/* ========== Register definition for SSC peripheral ========== */
#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */
#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */
#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */
#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */
#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */
#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
#endif /* _SAM3U_SSC_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_SUPC_INSTANCE_
#define _SAM3U_SUPC_INSTANCE_
/* ========== Register definition for SUPC peripheral ========== */
#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */
#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */
#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */
#endif /* _SAM3U_SUPC_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_TC0_INSTANCE_
#define _SAM3U_TC0_INSTANCE_
/* ========== Register definition for TC0 peripheral ========== */
#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400800C0U) /**< \brief (TC0) Block Control Register */
#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400800C4U) /**< \brief (TC0) Block Mode Register */
#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
#endif /* _SAM3U_TC0_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_TWI0_INSTANCE_
#define _SAM3U_TWI0_INSTANCE_
/* ========== Register definition for TWI0 peripheral ========== */
#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40084000U) /**< \brief (TWI0) Control Register */
#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40084004U) /**< \brief (TWI0) Master Mode Register */
#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40084008U) /**< \brief (TWI0) Slave Mode Register */
#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4008400CU) /**< \brief (TWI0) Internal Address Register */
#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40084020U) /**< \brief (TWI0) Status Register */
#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40084030U) /**< \brief (TWI0) Receive Holding Register */
#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40084104U) /**< \brief (TWI0) Receive Counter Register */
#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40084120U) /**< \brief (TWI0) Transfer Control Register */
#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40084124U) /**< \brief (TWI0) Transfer Status Register */
#endif /* _SAM3U_TWI0_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_TWI1_INSTANCE_
#define _SAM3U_TWI1_INSTANCE_
/* ========== Register definition for TWI1 peripheral ========== */
#define REG_TWI1_CR REG_ACCESS(WoReg, 0x40088000U) /**< \brief (TWI1) Control Register */
#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x40088004U) /**< \brief (TWI1) Master Mode Register */
#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x40088008U) /**< \brief (TWI1) Slave Mode Register */
#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4008800CU) /**< \brief (TWI1) Internal Address Register */
#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
#define REG_TWI1_SR REG_ACCESS(RoReg, 0x40088020U) /**< \brief (TWI1) Status Register */
#define REG_TWI1_IER REG_ACCESS(WoReg, 0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x40088030U) /**< \brief (TWI1) Receive Holding Register */
#define REG_TWI1_THR REG_ACCESS(WoReg, 0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x40088104U) /**< \brief (TWI1) Receive Counter Register */
#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x40088120U) /**< \brief (TWI1) Transfer Control Register */
#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x40088124U) /**< \brief (TWI1) Transfer Status Register */
#endif /* _SAM3U_TWI1_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_UART_INSTANCE_
#define _SAM3U_UART_INSTANCE_
/* ========== Register definition for UART peripheral ========== */
#define REG_UART_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART) Control Register */
#define REG_UART_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART) Mode Register */
#define REG_UART_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART) Interrupt Enable Register */
#define REG_UART_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART) Interrupt Disable Register */
#define REG_UART_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART) Interrupt Mask Register */
#define REG_UART_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART) Status Register */
#define REG_UART_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART) Receive Holding Register */
#define REG_UART_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART) Transmit Holding Register */
#define REG_UART_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */
#define REG_UART_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART) Receive Pointer Register */
#define REG_UART_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART) Receive Counter Register */
#define REG_UART_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART) Transmit Pointer Register */
#define REG_UART_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART) Transmit Counter Register */
#define REG_UART_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */
#define REG_UART_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART) Receive Next Counter Register */
#define REG_UART_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */
#define REG_UART_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */
#define REG_UART_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART) Transfer Control Register */
#define REG_UART_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART) Transfer Status Register */
#endif /* _SAM3U_UART_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_UDPHS_INSTANCE_
#define _SAM3U_UDPHS_INSTANCE_
/* ========== Register definition for UDPHS peripheral ========== */
#define REG_UDPHS_CTRL REG_ACCESS(RwReg, 0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */
#define REG_UDPHS_FNUM REG_ACCESS(RoReg, 0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */
#define REG_UDPHS_IEN REG_ACCESS(RwReg, 0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */
#define REG_UDPHS_INTSTA REG_ACCESS(RoReg, 0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */
#define REG_UDPHS_CLRINT REG_ACCESS(WoReg, 0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */
#define REG_UDPHS_EPTRST REG_ACCESS(WoReg, 0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */
#define REG_UDPHS_TST REG_ACCESS(RwReg, 0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */
#define REG_UDPHS_IPNAME1 REG_ACCESS(RoReg, 0x400A40F0U) /**< \brief (UDPHS) UDPHS Name1 Register */
#define REG_UDPHS_IPNAME2 REG_ACCESS(RoReg, 0x400A40F4U) /**< \brief (UDPHS) UDPHS Name2 Register */
#define REG_UDPHS_IPFEATURES REG_ACCESS(RoReg, 0x400A40F8U) /**< \brief (UDPHS) UDPHS Features Register */
#define REG_UDPHS_EPTCFG0 REG_ACCESS(RwReg, 0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */
#define REG_UDPHS_EPTCTLENB0 REG_ACCESS(WoReg, 0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */
#define REG_UDPHS_EPTCTLDIS0 REG_ACCESS(WoReg, 0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */
#define REG_UDPHS_EPTCTL0 REG_ACCESS(RoReg, 0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */
#define REG_UDPHS_EPTSETSTA0 REG_ACCESS(WoReg, 0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */
#define REG_UDPHS_EPTCLRSTA0 REG_ACCESS(WoReg, 0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */
#define REG_UDPHS_EPTSTA0 REG_ACCESS(RoReg, 0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */
#define REG_UDPHS_EPTCFG1 REG_ACCESS(RwReg, 0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */
#define REG_UDPHS_EPTCTLENB1 REG_ACCESS(WoReg, 0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */
#define REG_UDPHS_EPTCTLDIS1 REG_ACCESS(WoReg, 0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */
#define REG_UDPHS_EPTCTL1 REG_ACCESS(RoReg, 0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */
#define REG_UDPHS_EPTSETSTA1 REG_ACCESS(WoReg, 0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */
#define REG_UDPHS_EPTCLRSTA1 REG_ACCESS(WoReg, 0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */
#define REG_UDPHS_EPTSTA1 REG_ACCESS(RoReg, 0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */
#define REG_UDPHS_EPTCFG2 REG_ACCESS(RwReg, 0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */
#define REG_UDPHS_EPTCTLENB2 REG_ACCESS(WoReg, 0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */
#define REG_UDPHS_EPTCTLDIS2 REG_ACCESS(WoReg, 0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */
#define REG_UDPHS_EPTCTL2 REG_ACCESS(RoReg, 0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */
#define REG_UDPHS_EPTSETSTA2 REG_ACCESS(WoReg, 0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */
#define REG_UDPHS_EPTCLRSTA2 REG_ACCESS(WoReg, 0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */
#define REG_UDPHS_EPTSTA2 REG_ACCESS(RoReg, 0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */
#define REG_UDPHS_EPTCFG3 REG_ACCESS(RwReg, 0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */
#define REG_UDPHS_EPTCTLENB3 REG_ACCESS(WoReg, 0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */
#define REG_UDPHS_EPTCTLDIS3 REG_ACCESS(WoReg, 0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */
#define REG_UDPHS_EPTCTL3 REG_ACCESS(RoReg, 0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */
#define REG_UDPHS_EPTSETSTA3 REG_ACCESS(WoReg, 0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */
#define REG_UDPHS_EPTCLRSTA3 REG_ACCESS(WoReg, 0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */
#define REG_UDPHS_EPTSTA3 REG_ACCESS(RoReg, 0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */
#define REG_UDPHS_EPTCFG4 REG_ACCESS(RwReg, 0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */
#define REG_UDPHS_EPTCTLENB4 REG_ACCESS(WoReg, 0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */
#define REG_UDPHS_EPTCTLDIS4 REG_ACCESS(WoReg, 0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */
#define REG_UDPHS_EPTCTL4 REG_ACCESS(RoReg, 0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */
#define REG_UDPHS_EPTSETSTA4 REG_ACCESS(WoReg, 0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */
#define REG_UDPHS_EPTCLRSTA4 REG_ACCESS(WoReg, 0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */
#define REG_UDPHS_EPTSTA4 REG_ACCESS(RoReg, 0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */
#define REG_UDPHS_EPTCFG5 REG_ACCESS(RwReg, 0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */
#define REG_UDPHS_EPTCTLENB5 REG_ACCESS(WoReg, 0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */
#define REG_UDPHS_EPTCTLDIS5 REG_ACCESS(WoReg, 0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */
#define REG_UDPHS_EPTCTL5 REG_ACCESS(RoReg, 0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */
#define REG_UDPHS_EPTSETSTA5 REG_ACCESS(WoReg, 0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */
#define REG_UDPHS_EPTCLRSTA5 REG_ACCESS(WoReg, 0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */
#define REG_UDPHS_EPTSTA5 REG_ACCESS(RoReg, 0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */
#define REG_UDPHS_EPTCFG6 REG_ACCESS(RwReg, 0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */
#define REG_UDPHS_EPTCTLENB6 REG_ACCESS(WoReg, 0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */
#define REG_UDPHS_EPTCTLDIS6 REG_ACCESS(WoReg, 0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */
#define REG_UDPHS_EPTCTL6 REG_ACCESS(RoReg, 0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */
#define REG_UDPHS_EPTSETSTA6 REG_ACCESS(WoReg, 0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */
#define REG_UDPHS_EPTCLRSTA6 REG_ACCESS(WoReg, 0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */
#define REG_UDPHS_EPTSTA6 REG_ACCESS(RoReg, 0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */
#define REG_UDPHS_DMANXTDSC0 REG_ACCESS(RwReg, 0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */
#define REG_UDPHS_DMAADDRESS0 REG_ACCESS(RwReg, 0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */
#define REG_UDPHS_DMACONTROL0 REG_ACCESS(RwReg, 0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */
#define REG_UDPHS_DMASTATUS0 REG_ACCESS(RwReg, 0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */
#define REG_UDPHS_DMANXTDSC1 REG_ACCESS(RwReg, 0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */
#define REG_UDPHS_DMAADDRESS1 REG_ACCESS(RwReg, 0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */
#define REG_UDPHS_DMACONTROL1 REG_ACCESS(RwReg, 0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */
#define REG_UDPHS_DMASTATUS1 REG_ACCESS(RwReg, 0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */
#define REG_UDPHS_DMANXTDSC2 REG_ACCESS(RwReg, 0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */
#define REG_UDPHS_DMAADDRESS2 REG_ACCESS(RwReg, 0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */
#define REG_UDPHS_DMACONTROL2 REG_ACCESS(RwReg, 0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */
#define REG_UDPHS_DMASTATUS2 REG_ACCESS(RwReg, 0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */
#define REG_UDPHS_DMANXTDSC3 REG_ACCESS(RwReg, 0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */
#define REG_UDPHS_DMAADDRESS3 REG_ACCESS(RwReg, 0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */
#define REG_UDPHS_DMACONTROL3 REG_ACCESS(RwReg, 0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */
#define REG_UDPHS_DMASTATUS3 REG_ACCESS(RwReg, 0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */
#define REG_UDPHS_DMANXTDSC4 REG_ACCESS(RwReg, 0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */
#define REG_UDPHS_DMAADDRESS4 REG_ACCESS(RwReg, 0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */
#define REG_UDPHS_DMACONTROL4 REG_ACCESS(RwReg, 0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */
#define REG_UDPHS_DMASTATUS4 REG_ACCESS(RwReg, 0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */
#define REG_UDPHS_DMANXTDSC5 REG_ACCESS(RwReg, 0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */
#define REG_UDPHS_DMAADDRESS5 REG_ACCESS(RwReg, 0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */
#define REG_UDPHS_DMACONTROL5 REG_ACCESS(RwReg, 0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */
#define REG_UDPHS_DMASTATUS5 REG_ACCESS(RwReg, 0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */
#endif /* _SAM3U_UDPHS_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_USART0_INSTANCE_
#define _SAM3U_USART0_INSTANCE_
/* ========== Register definition for USART0 peripheral ========== */
#define REG_USART0_CR REG_ACCESS(WoReg, 0x40090000U) /**< \brief (USART0) Control Register */
#define REG_USART0_MR REG_ACCESS(RwReg, 0x40090004U) /**< \brief (USART0) Mode Register */
#define REG_USART0_IER REG_ACCESS(WoReg, 0x40090008U) /**< \brief (USART0) Interrupt Enable Register */
#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */
#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40090010U) /**< \brief (USART0) Interrupt Mask Register */
#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40090014U) /**< \brief (USART0) Channel Status Register */
#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40090018U) /**< \brief (USART0) Receiver Holding Register */
#define REG_USART0_THR REG_ACCESS(WoReg, 0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */
#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */
#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40090024U) /**< \brief (USART0) Receiver Time-out Register */
#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */
#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40090040U) /**< \brief (USART0) FI DI Ratio Register */
#define REG_USART0_NER REG_ACCESS(RoReg, 0x40090044U) /**< \brief (USART0) Number of Errors Register */
#define REG_USART0_IF REG_ACCESS(RwReg, 0x4009004CU) /**< \brief (USART0) IrDA Filter Register */
#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */
#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400900E8U) /**< \brief (USART0) Write Protect Status Register */
#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40090100U) /**< \brief (USART0) Receive Pointer Register */
#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40090104U) /**< \brief (USART0) Receive Counter Register */
#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40090108U) /**< \brief (USART0) Transmit Pointer Register */
#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4009010CU) /**< \brief (USART0) Transmit Counter Register */
#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */
#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40090114U) /**< \brief (USART0) Receive Next Counter Register */
#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */
#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */
#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40090120U) /**< \brief (USART0) Transfer Control Register */
#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40090124U) /**< \brief (USART0) Transfer Status Register */
#endif /* _SAM3U_USART0_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_USART1_INSTANCE_
#define _SAM3U_USART1_INSTANCE_
/* ========== Register definition for USART1 peripheral ========== */
#define REG_USART1_CR REG_ACCESS(WoReg, 0x40094000U) /**< \brief (USART1) Control Register */
#define REG_USART1_MR REG_ACCESS(RwReg, 0x40094004U) /**< \brief (USART1) Mode Register */
#define REG_USART1_IER REG_ACCESS(WoReg, 0x40094008U) /**< \brief (USART1) Interrupt Enable Register */
#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */
#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40094010U) /**< \brief (USART1) Interrupt Mask Register */
#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40094014U) /**< \brief (USART1) Channel Status Register */
#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40094018U) /**< \brief (USART1) Receiver Holding Register */
#define REG_USART1_THR REG_ACCESS(WoReg, 0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */
#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */
#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40094024U) /**< \brief (USART1) Receiver Time-out Register */
#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */
#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40094040U) /**< \brief (USART1) FI DI Ratio Register */
#define REG_USART1_NER REG_ACCESS(RoReg, 0x40094044U) /**< \brief (USART1) Number of Errors Register */
#define REG_USART1_IF REG_ACCESS(RwReg, 0x4009404CU) /**< \brief (USART1) IrDA Filter Register */
#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */
#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400940E8U) /**< \brief (USART1) Write Protect Status Register */
#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40094100U) /**< \brief (USART1) Receive Pointer Register */
#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40094104U) /**< \brief (USART1) Receive Counter Register */
#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40094108U) /**< \brief (USART1) Transmit Pointer Register */
#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4009410CU) /**< \brief (USART1) Transmit Counter Register */
#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */
#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40094114U) /**< \brief (USART1) Receive Next Counter Register */
#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */
#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */
#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40094120U) /**< \brief (USART1) Transfer Control Register */
#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40094124U) /**< \brief (USART1) Transfer Status Register */
#endif /* _SAM3U_USART1_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_USART2_INSTANCE_
#define _SAM3U_USART2_INSTANCE_
/* ========== Register definition for USART2 peripheral ========== */
#define REG_USART2_CR REG_ACCESS(WoReg, 0x40098000U) /**< \brief (USART2) Control Register */
#define REG_USART2_MR REG_ACCESS(RwReg, 0x40098004U) /**< \brief (USART2) Mode Register */
#define REG_USART2_IER REG_ACCESS(WoReg, 0x40098008U) /**< \brief (USART2) Interrupt Enable Register */
#define REG_USART2_IDR REG_ACCESS(WoReg, 0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */
#define REG_USART2_IMR REG_ACCESS(RoReg, 0x40098010U) /**< \brief (USART2) Interrupt Mask Register */
#define REG_USART2_CSR REG_ACCESS(RoReg, 0x40098014U) /**< \brief (USART2) Channel Status Register */
#define REG_USART2_RHR REG_ACCESS(RoReg, 0x40098018U) /**< \brief (USART2) Receiver Holding Register */
#define REG_USART2_THR REG_ACCESS(WoReg, 0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */
#define REG_USART2_BRGR REG_ACCESS(RwReg, 0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */
#define REG_USART2_RTOR REG_ACCESS(RwReg, 0x40098024U) /**< \brief (USART2) Receiver Time-out Register */
#define REG_USART2_TTGR REG_ACCESS(RwReg, 0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */
#define REG_USART2_FIDI REG_ACCESS(RwReg, 0x40098040U) /**< \brief (USART2) FI DI Ratio Register */
#define REG_USART2_NER REG_ACCESS(RoReg, 0x40098044U) /**< \brief (USART2) Number of Errors Register */
#define REG_USART2_IF REG_ACCESS(RwReg, 0x4009804CU) /**< \brief (USART2) IrDA Filter Register */
#define REG_USART2_MAN REG_ACCESS(RwReg, 0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
#define REG_USART2_WPMR REG_ACCESS(RwReg, 0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */
#define REG_USART2_WPSR REG_ACCESS(RoReg, 0x400980E8U) /**< \brief (USART2) Write Protect Status Register */
#define REG_USART2_RPR REG_ACCESS(RwReg, 0x40098100U) /**< \brief (USART2) Receive Pointer Register */
#define REG_USART2_RCR REG_ACCESS(RwReg, 0x40098104U) /**< \brief (USART2) Receive Counter Register */
#define REG_USART2_TPR REG_ACCESS(RwReg, 0x40098108U) /**< \brief (USART2) Transmit Pointer Register */
#define REG_USART2_TCR REG_ACCESS(RwReg, 0x4009810CU) /**< \brief (USART2) Transmit Counter Register */
#define REG_USART2_RNPR REG_ACCESS(RwReg, 0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */
#define REG_USART2_RNCR REG_ACCESS(RwReg, 0x40098114U) /**< \brief (USART2) Receive Next Counter Register */
#define REG_USART2_TNPR REG_ACCESS(RwReg, 0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */
#define REG_USART2_TNCR REG_ACCESS(RwReg, 0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */
#define REG_USART2_PTCR REG_ACCESS(WoReg, 0x40098120U) /**< \brief (USART2) Transfer Control Register */
#define REG_USART2_PTSR REG_ACCESS(RoReg, 0x40098124U) /**< \brief (USART2) Transfer Status Register */
#endif /* _SAM3U_USART2_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_USART3_INSTANCE_
#define _SAM3U_USART3_INSTANCE_
/* ========== Register definition for USART3 peripheral ========== */
#define REG_USART3_CR REG_ACCESS(WoReg, 0x4009C000U) /**< \brief (USART3) Control Register */
#define REG_USART3_MR REG_ACCESS(RwReg, 0x4009C004U) /**< \brief (USART3) Mode Register */
#define REG_USART3_IER REG_ACCESS(WoReg, 0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
#define REG_USART3_IDR REG_ACCESS(WoReg, 0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
#define REG_USART3_IMR REG_ACCESS(RoReg, 0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
#define REG_USART3_CSR REG_ACCESS(RoReg, 0x4009C014U) /**< \brief (USART3) Channel Status Register */
#define REG_USART3_RHR REG_ACCESS(RoReg, 0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
#define REG_USART3_THR REG_ACCESS(WoReg, 0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
#define REG_USART3_BRGR REG_ACCESS(RwReg, 0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
#define REG_USART3_RTOR REG_ACCESS(RwReg, 0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
#define REG_USART3_TTGR REG_ACCESS(RwReg, 0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
#define REG_USART3_FIDI REG_ACCESS(RwReg, 0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
#define REG_USART3_NER REG_ACCESS(RoReg, 0x4009C044U) /**< \brief (USART3) Number of Errors Register */
#define REG_USART3_IF REG_ACCESS(RwReg, 0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
#define REG_USART3_MAN REG_ACCESS(RwReg, 0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
#define REG_USART3_WPMR REG_ACCESS(RwReg, 0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
#define REG_USART3_WPSR REG_ACCESS(RoReg, 0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
#define REG_USART3_RPR REG_ACCESS(RwReg, 0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
#define REG_USART3_RCR REG_ACCESS(RwReg, 0x4009C104U) /**< \brief (USART3) Receive Counter Register */
#define REG_USART3_TPR REG_ACCESS(RwReg, 0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
#define REG_USART3_TCR REG_ACCESS(RwReg, 0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
#define REG_USART3_RNPR REG_ACCESS(RwReg, 0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
#define REG_USART3_RNCR REG_ACCESS(RwReg, 0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
#define REG_USART3_TNPR REG_ACCESS(RwReg, 0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
#define REG_USART3_TNCR REG_ACCESS(RwReg, 0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
#define REG_USART3_PTCR REG_ACCESS(WoReg, 0x4009C120U) /**< \brief (USART3) Transfer Control Register */
#define REG_USART3_PTSR REG_ACCESS(RoReg, 0x4009C124U) /**< \brief (USART3) Transfer Status Register */
#endif /* _SAM3U_USART3_INSTANCE_ */

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/* %ATMEL_LICENCE% */
#ifndef _SAM3U_WDT_INSTANCE_
#define _SAM3U_WDT_INSTANCE_
/* ========== Register definition for WDT peripheral ========== */
#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (WDT) Control Register */
#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1254U) /**< \brief (WDT) Mode Register */
#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (WDT) Status Register */
#endif /* _SAM3U_WDT_INSTANCE_ */