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22 lines
1.4 KiB
C
22 lines
1.4 KiB
C
/* %ATMEL_LICENCE% */
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#ifndef _SAM3U_RTC_INSTANCE_
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#define _SAM3U_RTC_INSTANCE_
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/* ========== Register definition for RTC peripheral ========== */
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#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1260U) /**< \brief (RTC) Control Register */
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#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1264U) /**< \brief (RTC) Mode Register */
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#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1268U) /**< \brief (RTC) Time Register */
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#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E126CU) /**< \brief (RTC) Calendar Register */
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#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (RTC) Time Alarm Register */
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#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
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#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1278U) /**< \brief (RTC) Status Register */
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#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
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#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
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#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
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#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
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#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E128CU) /**< \brief (RTC) Valid Entry Register */
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#define REG_RTC_WPMR REG_ACCESS(RwReg, 0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */
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#endif /* _SAM3U_RTC_INSTANCE_ */
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