mirror of
https://github.com/esp8266/Arduino.git
synced 2025-06-03 07:02:28 +03:00
register and clock changes
This commit is contained in:
John Doe
parent
1501818c67
commit
6ab3c76e03
@ -262,7 +262,7 @@ void uart_set_baudrate(uart_t* uart, int baud_rate) {
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if(uart == 0)
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return;
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uart->baud_rate = baud_rate;
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USD(uart->uart_nr) = (80000000UL / uart->baud_rate);
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USD(uart->uart_nr) = (ESP8266_CLOCK / uart->baud_rate);
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}
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int uart_get_baudrate(uart_t* uart) {
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@ -359,7 +359,7 @@ void uart_swap(uart_t* uart) {
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if(uart->txPin == 1 && uart->rxPin == 3) {
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pinMode(15, FUNCTION_4); //TX
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pinMode(13, FUNCTION_4); //RX
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USWAP |= (1 << USWAP0);
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IOSWAP |= (1 << IOSWAPU0);
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pinMode(1, INPUT); //TX
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pinMode(3, INPUT); //RX
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uart->rxPin = 13;
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@ -367,7 +367,7 @@ void uart_swap(uart_t* uart) {
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} else {
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pinMode(1, SPECIAL); //TX
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pinMode(3, SPECIAL); //RX
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USWAP &= ~(1 << USWAP0);
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IOSWAP &= ~(1 << IOSWAPU0);
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pinMode(15, INPUT); //TX
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pinMode(13, INPUT); //RX
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uart->rxPin = 3;
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@ -83,7 +83,7 @@ void prep_pwm_steps(){
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pwm_steps_len = pwm_temp_steps_len;
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ets_memcpy(pwm_steps, pwm_temp_steps, (pwm_temp_steps_len + 1) * 2);
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ets_memcpy(pwm_steps_mask, pwm_temp_masks, pwm_temp_steps_len * 4);
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pwm_multiplier = F_CPU/(PWMRANGE * pwm_freq);
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pwm_multiplier = ESP8266_CLOCK/(PWMRANGE * pwm_freq);
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ETS_FRC1_INTR_ENABLE();
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}
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@ -25,6 +25,15 @@
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#define ESP8266_REG(addr) *((volatile uint32_t *)(0x60000000+(addr)))
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#define ESP8266_DREG(addr) *((volatile uint32_t *)(0x3FF00000+(addr)))
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#define ESP8266_CLOCK 80000000UL
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//CPU Register
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#define CPU2X ESP8266_DREG(0x14) //when bit 0 is set, F_CPU = 160MHz
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//OTP Registers
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#define MAC0 ESP8266_DREG(0x50)
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#define MAC1 ESP8266_DREG(0x54)
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#define CHIPID ESP8266_DREG(0x58)
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//GPIO (0-15) Control Registers
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#define GPO ESP8266_REG(0x300) //GPIO_OUT R/W (Output Level)
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@ -149,20 +158,26 @@ extern uint8_t esp8266_gpioToFn[16];
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#define TCIT 0 //Interrupt Type 0:edge, 1:level
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//RTC Registers
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#define RTCMEM(i) ESP8266_REG(0x1100 + (((i) & 0xFF) * 4)) //RTC RAM 768 bytes, 192 registers
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#define RTCSV ESP8266_REG(0x704) //RTC SLEEP COUNTER Target Value
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#define RTCCV ESP8266_REG(0x71C) //RTC SLEEP COUNTER Value
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#define RTCIS ESP8266_REG(0x720) //RTC INT Status
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#define RTCIC ESP8266_REG(0x724) //RTC INT Clear
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#define RTCIE ESP8266_REG(0x728) //RTC INT Enable
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#define RTCS0 ESP8266_REG(0x730) //RTC SCRATCH 0
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#define RTCS1 ESP8266_REG(0x734) //RTC SCRATCH 1
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#define RTCS2 ESP8266_REG(0x738) //RTC SCRATCH 2
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#define RTCS3 ESP8266_REG(0x73C) //RTC SCRATCH 3
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//UART SWAP Register
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#define USWAP ESP8266_DREG(0x28)
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#define USWAP0 2 //BIT 2 swaps UART 0
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//IO SWAP Register
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#define IOSWAP ESP8266_DREG(0x28)
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#define IOSWAPU 0 //Swaps UART
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#define IOSWAPS 1 //Swaps SPI
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#define IOSWAPU0 2 //Swaps UART 0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)
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#define IOSWAPU1 3 //Swaps UART 1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)
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#define IOSWAPHS 5 //Sets HSPI with higher prio
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#define IOSWAP2HS 6 //Sets Two SPI Masters on HSPI
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#define IOSWAP2CS 7 //Sets Two SPI Masters on CSPI
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//UART INT Status
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#define UIS ESP8266_DREG(0x20020)
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#define UIS0 0
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#define UIS1 2
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//UART 0 Registers
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#define U0F ESP8266_REG(0x000) //UART FIFO
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@ -227,9 +242,9 @@ extern uint8_t esp8266_gpioToFn[16];
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#define UIFF 0 //RX FIFO Full
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//UART STATUS Registers Bits
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#define USTX 31 //TX PIN Level
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#define USRTS 30 //RTS PIN Level
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#define USDTR 39 //DTR PIN Level
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#define USTX 31 //TX PIN Level
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#define USRTS 30 //RTS PIN Level
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#define USDTR 39 //DTR PIN Level
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#define USTXC 16 //TX FIFO COUNT (8bit)
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#define USRXD 15 //RX PIN Level
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#define USCTS 14 //CTS PIN Level
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@ -237,35 +252,39 @@ extern uint8_t esp8266_gpioToFn[16];
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#define USRXC 0 //RX FIFO COUNT (8bit)
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//UART CONF0 Registers Bits
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#define UCDTRI 24 //Invert DTR
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#define UCRTSI 23 //Invert RTS
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#define UCTXI 22 //Invert TX
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#define UCDSRI 21 //Invert DSR
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#define UCCTSI 20 //Invert CTS
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#define UCRXI 19 //Invert RX
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#define UCDTRI 24 //Invert DTR
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#define UCRTSI 23 //Invert RTS
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#define UCTXI 22 //Invert TX
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#define UCDSRI 21 //Invert DSR
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#define UCCTSI 20 //Invert CTS
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#define UCRXI 19 //Invert RX
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#define UCTXRST 18 //Reset TX FIFO
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#define UCRXRST 17 //Reset RX FIFO
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#define UCTXHFE 15 //TX Harware Flow Enable
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#define UCLBE 14 //LoopBack Enable
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#define UCBRK 8 //Send Break on the TX line
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#define UCLBE 14 //LoopBack Enable
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#define UCBRK 8 //Send Break on the TX line
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#define UCSWDTR 7 //Set this bit to assert DTR
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#define UCSWRTS 6 //Set this bit to assert RTS
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#define UCSBN 4 //StopBits Count (2bit) 0:disable, 1:1bit, 2:1.5bit, 3:2bit
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#define UCBN 2 //DataBits Count (2bin) 0:5bit, 1:6bit, 2:7bit, 3:8bit
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#define UCPAE 1 //Parity Enable
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#define UCPA 0 //Parity 0:even, 1:odd
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#define UCSBN 4 //StopBits Count (2bit) 0:disable, 1:1bit, 2:1.5bit, 3:2bit
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#define UCBN 2 //DataBits Count (2bin) 0:5bit, 1:6bit, 2:7bit, 3:8bit
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#define UCPAE 1 //Parity Enable
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#define UCPA 0 //Parity 0:even, 1:odd
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//UART CONF1 Registers Bits
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#define UCTOE 31 //RX TimeOut Enable
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#define UCTOT 24 //RX TimeOut Treshold (7bit)
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#define UCTOE 31 //RX TimeOut Enable
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#define UCTOT 24 //RX TimeOut Treshold (7bit)
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#define UCRXHFE 23 //RX Harware Flow Enable
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#define UCRXHFT 16 //RX Harware Flow Treshold (7bit)
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#define UCFET 8 //TX FIFO Empty Treshold (7bit)
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#define UCFFT 0 //RX FIFO Full Treshold (7bit)
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#define UCFET 8 //TX FIFO Empty Treshold (7bit)
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#define UCFFT 0 //RX FIFO Full Treshold (7bit)
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//WDT Register used for UART
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#define WDTRST ESP8266_REG(0x914)
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#define WDT_RESET() (WDTRST = 0x73)
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//WDT Feed (the dog) Register
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#define WDTFEED ESP8266_REG(0x914)
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#define WDT_FEED() (WDTFEED = 0x73)
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//SPI_READY
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#define SPIRDY ESP8266_DREG(0x0C)
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#define SPIBUSY 9 //wait SPI idle
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//SPI0 Registers (SPI0 is used for the flash)
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#define SPI0CMD ESP8266_REG(0x200)
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@ -5,14 +5,14 @@
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0x3FF00000 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF00004 | 00000000000000000000000000000101 | 0x00000005 | 5 | | TEIE
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0x3FF00008 | 00000000000000000000100000001111 | 0x0000080F | 2063 | . |
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0x3FF0000C | 00000100000000000000000100000010 | 0x04000102 | 67109122 | |
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0x3FF0000C | 00000100000000000000000100000010 | 0x04000102 | 67109122 | | SPIRDY
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0x3FF00010 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF00014 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF00014 | 00000000000000000000000000000000 | 0x00000000 | 0 | | CPU2X
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0x3FF00018 | 11111111111111110000000011111111 | 0xFFFF00FF | 4294902015 | .. . |
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0x3FF0001C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF00020 | 00000000000000000000000000010000 | 0x00000010 | 16 | . | SPIIR
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0x3FF00024 | 00000000000000000000000000011010 | 0x0000001A | 26 | . |
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0x3FF00028 | 00000000000000000000000000000000 | 0x00000000 | 0 | | USWAP
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0x3FF00028 | 00000000000000000000000000000000 | 0x00000000 | 0 | | IOSWAP
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0x3FF0002C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF00030 | 00000000000000000100000001000000 | 0x00004040 | 16448 | @@ |
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0x3FF00034 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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@ -22,9 +22,9 @@
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0x3FF00044 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF00048 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF0004C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF00050 | 10011101111011100000000000000000 | 0x9DEE0000 | 2649620480 | .. |
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0x3FF00054 | 00000010000000001001110011000010 | 0x02009CC2 | 33594562 | .. |
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0x3FF00058 | 00000000000000001010000000000000 | 0x0000A000 | 40960 | . |
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0x3FF00050 | 10011101111011100000000000000000 | 0x9DEE0000 | 2649620480 | .. | MAC0
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0x3FF00054 | 00000010000000001001110011000010 | 0x02009CC2 | 33594562 | .. | MAC1
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0x3FF00058 | 00000000000000001010000000000000 | 0x0000A000 | 40960 | . | CHIPID
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0x3FF0005C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF00060 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x3FF00064 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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@ -687,14 +687,13 @@
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0x60000908 | 00000000000000000000000000001011 | 0x0000000B | 11 | |
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0x6000090C | 00000000000000111001000001110010 | 0x00039072 | 233586 | r |
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0x60000910 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x60000914 | 00000000000000000000000000000000 | 0x00000000 | 0 | | WDTRST
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0x60000914 | 00000000000000000000000000000000 | 0x00000000 | 0 | | WDTFEED
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0x60000918 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x6000091C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x60000920 | 00000000000000000000000000111001 | 0x00000039 | 57 | 9 |
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0x60000924 | 00000000000000000000000000001011 | 0x0000000B | 11 | |
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0x60000928 | 00000000000000000000000000001011 | 0x0000000B | 11 | |
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0x6000092C | 00000111100111110000110111101010 | 0x079F0DEA | 127864298 |
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ê|
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0x6000092C | 00000111100111110000110111101010 | 0x079F0DEA | 127864298 | ê |
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0x60000930 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x60000934 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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0x60000938 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
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@ -121,14 +121,14 @@ void SPIClass::setBitOrder(uint8_t bitOrder) {
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* @return
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*/
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static uint32_t ClkRegToFreq(spiClk_t * reg) {
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return (SPI_MAX_SPEED / ((reg->regPre + 1) * (reg->regN + 1)));
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return (ESP8266_CLOCK / ((reg->regPre + 1) * (reg->regN + 1)));
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}
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void SPIClass::setFrequency(uint32_t freq) {
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static uint32_t lastSetFrequency = 0;
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static uint32_t lastSetRegister = 0;
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if(freq >= SPI_MAX_SPEED) {
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if(freq >= ESP8266_CLOCK) {
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setClockDivider(0x80000000);
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return;
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}
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@ -164,7 +164,7 @@ void SPIClass::setFrequency(uint32_t freq) {
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reg.regN = calN;
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while(calPreVari++ <= 1) { // test different variants for Pre (we calculate in int so we miss the decimals, testing is the easyest and fastest way)
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calPre = (((SPI_MAX_SPEED / (reg.regN + 1)) / freq) - 1) + calPreVari;
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calPre = (((ESP8266_CLOCK / (reg.regN + 1)) / freq) - 1) + calPreVari;
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if(calPre > 0x1FFF) {
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reg.regPre = 0x1FFF; // 8191
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} else if(calPre <= 0) {
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@ -45,8 +45,6 @@
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#define SPI_CLOCK_DIV64 0x04fc1001 //250 KHz
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#endif
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#define SPI_MAX_SPEED (80000000L)
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const uint8_t SPI_MODE0 = 0x00; ///< CPOL: 0 CPHA: 0
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const uint8_t SPI_MODE1 = 0x01; ///< CPOL: 0 CPHA: 1
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const uint8_t SPI_MODE2 = 0x10; ///< CPOL: 1 CPHA: 0
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@ -39,11 +39,13 @@ typedef struct _ETSTIMER_ {
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typedef void (*int_handler_t)(void*);
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#define ETS_SPI_INUM 2
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#define ETS_SPI_INUM 2
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#define ETS_GPIO_INUM 4
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#define ETS_UART_INUM 5
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#define ETS_UART1_INUM 5
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#define ETS_CCOMPARE0_INUM 6
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#define ETS_SOFT_INUM 7
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#define ETS_WDT_INUM 8
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#define ETS_FRC_TIMER1_INUM 9 /* use edge*/
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#define ETS_INTR_LOCK() \
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