Merge pull request #433 from me-no-dev/esp8266

allow proper content length handling
2025-04-25 20:02:37 +03:00 · 2015-06-19 20:49:50 +03:00 · 2015-06-19 20:49:50 +03:00 · 5d4266a50e
commit 5d4266a50e
parent 432198f178 8ba054c6b0
5 changed files with 449 additions and 32 deletions
--- a/.gitignore
+++ b/.gitignore
@ -72,4 +72,3 @@ nbproject
 build/macosx/esptool-*-osx.zip

 build/macosx/dist/osx-xtensa-lx106-elf.tgz
-/hardware/esp8266com/esp8266/tools
--- a/libraries/ESP8266WebServer/src/ESP8266WebServer.cpp
+++ b/libraries/ESP8266WebServer/src/ESP8266WebServer.cpp
@ -140,11 +140,10 @@ void ESP8266WebServer::send(int code, const char* content_type, String content)
    content_type = "text/html";
  
  sendHeader("Content-Type", content_type, true);
-  if (_contentLength != CONTENT_LENGTH_UNKNOWN) {
-    size_t length = (_contentLength == CONTENT_LENGTH_NOT_SET) ? 
-                    content.length() : _contentLength;
-    String lengthStr(length);
-    sendHeader("Content-Length", lengthStr.c_str());
+  if (_contentLength != CONTENT_LENGTH_UNKNOWN && _contentLength != CONTENT_LENGTH_NOT_SET) {
+    sendHeader("Content-Length", String(_contentLength).c_str());
+  } else if(content.length() > 0){
+    sendHeader("Content-Length", String(content.length()).c_str());
  }
  sendHeader("Connection", "close");
  sendHeader("Access-Control-Allow-Origin", "*");
--- a/tools/sdk/include/ets_sys.h
+++ b/tools/sdk/include/ets_sys.h
@ -39,6 +39,7 @@ typedef struct _ETSTIMER_ {

 typedef void (*int_handler_t)(void*);

+#define ETS_SLC_INUM        1
 #define ETS_SPI_INUM        2
 #define ETS_GPIO_INUM       4
 #define ETS_UART_INUM       5
@ -54,6 +55,12 @@ typedef void (*int_handler_t)(void*);
 #define ETS_INTR_UNLOCK() \
    ets_intr_unlock()

+#define ETS_INTR_ENABLE(inum) \
+    ets_isr_unmask((1<<inum))
+
+#define ETS_INTR_DISABLE(inum) \
+    ets_isr_mask((1<<inum))
+
 inline uint32_t ETS_INTR_ENABLED(void)
 {
    uint32_t enabled;
@ -71,53 +78,64 @@ inline uint32_t ETS_INTR_PENDING(void)
 #define ETS_CCOMPARE0_INTR_ATTACH(func, arg) \
    ets_isr_attach(ETS_CCOMPARE0_INUM, (int_handler_t)(func), (void *)(arg))

+#define ETS_CCOMPARE0_ENABLE() \
+    ETS_INTR_ENABLE(ETS_CCOMPARE0_INUM)
+
+#define ETS_CCOMPARE0_DISABLE() \
+    ETS_INTR_DISABLE(ETS_CCOMPARE0_INUM)
+
+
 #define ETS_FRC_TIMER1_INTR_ATTACH(func, arg) \
    ets_isr_attach(ETS_FRC_TIMER1_INUM, (int_handler_t)(func), (void *)(arg))

 #define ETS_FRC_TIMER1_NMI_INTR_ATTACH(func) \
-	NmiTimSetFunc(func)
-	
+    NmiTimSetFunc(func)
+
+#define ETS_FRC1_INTR_ENABLE() \
+    ETS_INTR_ENABLE(ETS_FRC_TIMER1_INUM)
+
+#define ETS_FRC1_INTR_DISABLE() \
+    ETS_INTR_DISABLE(ETS_FRC_TIMER1_INUM)
+
+
 #define ETS_GPIO_INTR_ATTACH(func, arg) \
    ets_isr_attach(ETS_GPIO_INUM, (int_handler_t)(func), (void *)(arg))

+#define ETS_GPIO_INTR_ENABLE() \
+    ETS_INTR_ENABLE(ETS_GPIO_INUM)
+
+#define ETS_GPIO_INTR_DISABLE() \
+    ETS_INTR_DISABLE(ETS_GPIO_INUM)
+
+
 #define ETS_UART_INTR_ATTACH(func, arg) \
    ets_isr_attach(ETS_UART_INUM, (int_handler_t)(func), (void *)(arg))

-#define ETS_SPI_INTR_ATTACH(func, arg) \
-    ets_isr_attach(ETS_SPI_INUM, (int_handler_t)(func), (void *)(arg))
-
-#define ETS_INTR_ENABLE(inum) \
-    ets_isr_unmask((1<<inum))
-
-#define ETS_INTR_DISABLE(inum) \
-    ets_isr_mask((1<<inum))
-
-#define ETS_SPI_INTR_ENABLE() \
-    ETS_INTR_ENABLE(ETS_SPI_INUM)
-
 #define ETS_UART_INTR_ENABLE() \
    ETS_INTR_ENABLE(ETS_UART_INUM)

 #define ETS_UART_INTR_DISABLE() \
    ETS_INTR_DISABLE(ETS_UART_INUM)

-#define ETS_CCOMPARE0_ENABLE() \
-	ETS_INTR_ENABLE(ETS_CCOMPARE0_INUM)

-#define ETS_CCOMPARE0_DISABLE() \
-	ETS_INTR_DISABLE(ETS_CCOMPARE0_INUM)
+#define ETS_SPI_INTR_ATTACH(func, arg) \
+    ets_isr_attach(ETS_SPI_INUM, (int_handler_t)(func), (void *)(arg))

-#define ETS_FRC1_INTR_ENABLE() \
-	ETS_INTR_ENABLE(ETS_FRC_TIMER1_INUM)
+#define ETS_SPI_INTR_ENABLE() \
+    ETS_INTR_ENABLE(ETS_SPI_INUM)

-#define ETS_FRC1_INTR_DISABLE() \
-	ETS_INTR_DISABLE(ETS_FRC_TIMER1_INUM)
+#define ETS_SPI_INTR_DISABLE() \
+    ETS_INTR_DISABLE(ETS_SPI_INUM)

-#define ETS_GPIO_INTR_ENABLE() \
-    ETS_INTR_ENABLE(ETS_GPIO_INUM)

-#define ETS_GPIO_INTR_DISABLE() \
-    ETS_INTR_DISABLE(ETS_GPIO_INUM)
+#define ETS_SLC_INTR_ATTACH(func, arg) \
+    ets_isr_attach(ETS_SLC_INUM, (int_handler_t)(func), (void *)(arg))
+
+#define ETS_SLC_INTR_ENABLE() \
+    ETS_INTR_ENABLE(ETS_SLC_INUM)
+
+#define ETS_SLC_INTR_DISABLE() \
+    ETS_INTR_DISABLE(ETS_SLC_INUM)


 void *pvPortMalloc(size_t xWantedSize) __attribute__((malloc, alloc_size(1)));
--- a/tools/sdk/include/i2s_reg.h
+++ b/tools/sdk/include/i2s_reg.h
@ -0,0 +1,118 @@
+/*
+ *  Copyright (c) 2010 - 2011 Espressif System
+ *
+ */
+
+#ifndef I2S_REGISTER_H_
+#define I2S_REGISTER_H_
+
+#define DR_REG_I2S_BASE (0x60000e00)
+
+#define I2STXFIFO  (DR_REG_I2S_BASE + 0x0000)
+#define I2SRXFIFO  (DR_REG_I2S_BASE + 0x0004)
+#define I2SCONF  (DR_REG_I2S_BASE + 0x0008)
+#define I2S_BCK_DIV_NUM 0x0000003F
+#define I2S_BCK_DIV_NUM_S 22
+#define I2S_CLKM_DIV_NUM 0x0000003F
+#define I2S_CLKM_DIV_NUM_S 16
+#define I2S_BITS_MOD 0x0000000F
+#define I2S_BITS_MOD_S 12
+#define I2S_RECE_MSB_SHIFT (BIT(11))
+#define I2S_TRANS_MSB_SHIFT (BIT(10))
+#define I2S_I2S_RX_START (BIT(9))
+#define I2S_I2S_TX_START (BIT(8))
+#define I2S_MSB_RIGHT (BIT(7))
+#define I2S_RIGHT_FIRST (BIT(6))
+#define I2S_RECE_SLAVE_MOD (BIT(5))
+#define I2S_TRANS_SLAVE_MOD (BIT(4))
+#define I2S_I2S_RX_FIFO_RESET (BIT(3))
+#define I2S_I2S_TX_FIFO_RESET (BIT(2))
+#define I2S_I2S_RX_RESET (BIT(1))
+#define I2S_I2S_TX_RESET (BIT(0))
+#define I2S_I2S_RESET_MASK 0xf
+
+#define I2SINT_RAW (DR_REG_I2S_BASE + 0x000c)
+#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5))
+#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4))
+#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3))
+#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2))
+#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1))
+#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
+
+
+#define I2SINT_ST (DR_REG_I2S_BASE + 0x0010)
+#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5))
+#define I2S_I2S_TX_WFULL_INT_ST (BIT(4))
+#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3))
+#define I2S_I2S_RX_WFULL_INT_ST (BIT(2))
+#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1))
+#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0))
+
+#define I2SINT_ENA (DR_REG_I2S_BASE + 0x0014)
+#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5))
+#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4))
+#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3))
+#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2))
+#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1))
+#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
+
+#define I2SINT_CLR (DR_REG_I2S_BASE + 0x0018)
+#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5))
+#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4))
+#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3))
+#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2))
+#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1))
+#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0))
+
+#define I2STIMING (DR_REG_I2S_BASE + 0x001c)
+#define I2S_TRANS_BCK_IN_INV (BIT(22))
+#define I2S_RECE_DSYNC_SW (BIT(21))
+#define I2S_TRANS_DSYNC_SW (BIT(20))
+#define I2S_RECE_BCK_OUT_DELAY 0x00000003
+#define I2S_RECE_BCK_OUT_DELAY_S 18
+#define I2S_RECE_WS_OUT_DELAY 0x00000003
+#define I2S_RECE_WS_OUT_DELAY_S 16
+#define I2S_TRANS_SD_OUT_DELAY 0x00000003
+#define I2S_TRANS_SD_OUT_DELAY_S 14
+#define I2S_TRANS_WS_OUT_DELAY 0x00000003
+#define I2S_TRANS_WS_OUT_DELAY_S 12
+#define I2S_TRANS_BCK_OUT_DELAY 0x00000003
+#define I2S_TRANS_BCK_OUT_DELAY_S 10
+#define I2S_RECE_SD_IN_DELAY 0x00000003
+#define I2S_RECE_SD_IN_DELAY_S 8
+#define I2S_RECE_WS_IN_DELAY 0x00000003
+#define I2S_RECE_WS_IN_DELAY_S 6
+#define I2S_RECE_BCK_IN_DELAY 0x00000003
+#define I2S_RECE_BCK_IN_DELAY_S 4
+#define I2S_TRANS_WS_IN_DELAY 0x00000003
+#define I2S_TRANS_WS_IN_DELAY_S 2
+#define I2S_TRANS_BCK_IN_DELAY 0x00000003
+#define I2S_TRANS_BCK_IN_DELAY_S 0
+
+#define I2S_FIFO_CONF (DR_REG_I2S_BASE + 0x0020)
+#define I2S_I2S_RX_FIFO_MOD 0x00000007
+#define I2S_I2S_RX_FIFO_MOD_S 16
+#define I2S_I2S_TX_FIFO_MOD 0x00000007
+#define I2S_I2S_TX_FIFO_MOD_S 13
+#define I2S_I2S_DSCR_EN (BIT(12))
+#define I2S_I2S_TX_DATA_NUM 0x0000003F
+#define I2S_I2S_TX_DATA_NUM_S 6
+#define I2S_I2S_RX_DATA_NUM 0x0000003F
+#define I2S_I2S_RX_DATA_NUM_S 0
+
+
+#define I2SRXEOF_NUM (DR_REG_I2S_BASE + 0x0024)
+#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF
+#define I2S_I2S_RX_EOF_NUM_S 0
+
+#define I2SCONF_SIGLE_DATA (DR_REG_I2S_BASE + 0x0028)
+#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF
+#define I2S_I2S_SIGLE_DATA_S 0
+
+#define I2SCONF_CHAN (DR_REG_I2S_BASE + 0x002c)
+#define I2S_RX_CHAN_MOD 0x00000003
+#define I2S_RX_CHAN_MOD_S 3
+#define I2S_TX_CHAN_MOD 0x00000007
+#define I2S_TX_CHAN_MOD_S 0
+
+#endif
--- a/tools/sdk/include/slc_register.h
+++ b/tools/sdk/include/slc_register.h
@ -0,0 +1,283 @@
+//Generated at 2012-10-23 19:55:03
+/*
+ *  Copyright (c) 2010 - 2011 Espressif System
+ *
+ */
+
+#ifndef SLC_REGISTER_H_
+#define SLC_REGISTER_H_
+
+#define REG_SLC_BASE  0x60000B00
+//version value:32'h091700
+
+#define SLC_CONF0                                (REG_SLC_BASE + 0x0)
+#ifndef ESP_MAC_5
+#define SLC_MODE 0x00000003
+#define SLC_MODE_S 12
+#endif
+#define SLC_DATA_BURST_EN (BIT(9))
+#define SLC_DSCR_BURST_EN (BIT(8))
+#define SLC_RX_NO_RESTART_CLR (BIT(7))
+#define SLC_RX_AUTO_WRBACK (BIT(6))
+#define SLC_RX_LOOP_TEST (BIT(5))
+#define SLC_TX_LOOP_TEST (BIT(4))
+#define SLC_AHBM_RST (BIT(3))
+#define SLC_AHBM_FIFO_RST (BIT(2))
+#define SLC_RXLINK_RST (BIT(1))
+#define SLC_TXLINK_RST (BIT(0))
+
+#define SLC_INT_RAW                              (REG_SLC_BASE + 0x4)
+#define SLC_TX_DSCR_EMPTY_INT_RAW (BIT(21))
+#define SLC_RX_DSCR_ERR_INT_RAW (BIT(20))
+#define SLC_TX_DSCR_ERR_INT_RAW (BIT(19))
+#define SLC_TOHOST_INT_RAW (BIT(18))
+#define SLC_RX_EOF_INT_RAW (BIT(17))
+#define SLC_RX_DONE_INT_RAW (BIT(16))
+#define SLC_TX_EOF_INT_RAW (BIT(15))
+#define SLC_TX_DONE_INT_RAW (BIT(14))
+#define SLC_TOKEN1_1TO0_INT_RAW (BIT(13))
+#define SLC_TOKEN0_1TO0_INT_RAW (BIT(12))
+#define SLC_TX_OVF_INT_RAW (BIT(11))
+#define SLC_RX_UDF_INT_RAW (BIT(10))
+#define SLC_TX_START_INT_RAW (BIT(9))
+#define SLC_RX_START_INT_RAW (BIT(8))
+#define SLC_FRHOST_BIT7_INT_RAW (BIT(7))
+#define SLC_FRHOST_BIT6_INT_RAW (BIT(6))
+#define SLC_FRHOST_BIT5_INT_RAW (BIT(5))
+#define SLC_FRHOST_BIT4_INT_RAW (BIT(4))
+#define SLC_FRHOST_BIT3_INT_RAW (BIT(3))
+#define SLC_FRHOST_BIT2_INT_RAW (BIT(2))
+#define SLC_FRHOST_BIT1_INT_RAW (BIT(1))
+#define SLC_FRHOST_BIT0_INT_RAW (BIT(0))
+
+#define SLC_INT_STATUS                               (REG_SLC_BASE + 0x8)
+#define SLC_TX_DSCR_EMPTY_INT_ST (BIT(21))
+#define SLC_RX_DSCR_ERR_INT_ST (BIT(20))
+#define SLC_TX_DSCR_ERR_INT_ST (BIT(19))
+#define SLC_TOHOST_INT_ST (BIT(18))
+#define SLC_RX_EOF_INT_ST (BIT(17))
+#define SLC_RX_DONE_INT_ST (BIT(16))
+#define SLC_TX_EOF_INT_ST (BIT(15))
+#define SLC_TX_DONE_INT_ST (BIT(14))
+#define SLC_TOKEN1_1TO0_INT_ST (BIT(13))
+#define SLC_TOKEN0_1TO0_INT_ST (BIT(12))
+#define SLC_TX_OVF_INT_ST (BIT(11))
+#define SLC_RX_UDF_INT_ST (BIT(10))
+#define SLC_TX_START_INT_ST (BIT(9))
+#define SLC_RX_START_INT_ST (BIT(8))
+#define SLC_FRHOST_BIT7_INT_ST (BIT(7))
+#define SLC_FRHOST_BIT6_INT_ST (BIT(6))
+#define SLC_FRHOST_BIT5_INT_ST (BIT(5))
+#define SLC_FRHOST_BIT4_INT_ST (BIT(4))
+#define SLC_FRHOST_BIT3_INT_ST (BIT(3))
+#define SLC_FRHOST_BIT2_INT_ST (BIT(2))
+#define SLC_FRHOST_BIT1_INT_ST (BIT(1))
+#define SLC_FRHOST_BIT0_INT_ST (BIT(0))
+
+#define SLC_INT_ENA                              (REG_SLC_BASE + 0xC)
+#define SLC_TX_DSCR_EMPTY_INT_ENA (BIT(21))
+#define SLC_RX_DSCR_ERR_INT_ENA (BIT(20))
+#define SLC_TX_DSCR_ERR_INT_ENA (BIT(19))
+#define SLC_TOHOST_INT_ENA (BIT(18))
+#define SLC_RX_EOF_INT_ENA (BIT(17))
+#define SLC_RX_DONE_INT_ENA (BIT(16))
+#define SLC_TX_EOF_INT_ENA (BIT(15))
+#define SLC_TX_DONE_INT_ENA (BIT(14))
+#define SLC_TOKEN1_1TO0_INT_ENA (BIT(13))
+#define SLC_TOKEN0_1TO0_INT_ENA (BIT(12))
+#define SLC_TX_OVF_INT_ENA (BIT(11))
+#define SLC_RX_UDF_INT_ENA (BIT(10))
+#define SLC_TX_START_INT_ENA (BIT(9))
+#define SLC_RX_START_INT_ENA (BIT(8))
+#define SLC_FRHOST_BIT7_INT_ENA (BIT(7))
+#define SLC_FRHOST_BIT6_INT_ENA (BIT(6))
+#define SLC_FRHOST_BIT5_INT_ENA (BIT(5))
+#define SLC_FRHOST_BIT4_INT_ENA (BIT(4))
+#define SLC_FRHOST_BIT3_INT_ENA (BIT(3))
+#define SLC_FRHOST_BIT2_INT_ENA (BIT(2))
+#define SLC_FRHOST_BIT1_INT_ENA (BIT(1))
+#define SLC_FRHOST_BIT0_INT_ENA (BIT(0))
+
+#define SLC_FRHOST_BIT_INT_ENA_ALL  0xff
+
+#define SLC_INT_CLR                              (REG_SLC_BASE + 0x10)
+#define SLC_TX_DSCR_EMPTY_INT_CLR (BIT(21))
+#define SLC_RX_DSCR_ERR_INT_CLR (BIT(20))
+#define SLC_TX_DSCR_ERR_INT_CLR (BIT(19))
+#define SLC_TOHOST_INT_CLR (BIT(18))
+#define SLC_RX_EOF_INT_CLR (BIT(17))
+#define SLC_RX_DONE_INT_CLR (BIT(16))
+#define SLC_TX_EOF_INT_CLR (BIT(15))
+#define SLC_TX_DONE_INT_CLR (BIT(14))
+#define SLC_TOKEN1_1TO0_INT_CLR (BIT(13))
+#define SLC_TOKEN0_1TO0_INT_CLR (BIT(12))
+#define SLC_TX_OVF_INT_CLR (BIT(11))
+#define SLC_RX_UDF_INT_CLR (BIT(10))
+#define SLC_TX_START_INT_CLR (BIT(9))
+#define SLC_RX_START_INT_CLR (BIT(8))
+#define SLC_FRHOST_BIT7_INT_CLR (BIT(7))
+#define SLC_FRHOST_BIT6_INT_CLR (BIT(6))
+#define SLC_FRHOST_BIT5_INT_CLR (BIT(5))
+#define SLC_FRHOST_BIT4_INT_CLR (BIT(4))
+#define SLC_FRHOST_BIT3_INT_CLR (BIT(3))
+#define SLC_FRHOST_BIT2_INT_CLR (BIT(2))
+#define SLC_FRHOST_BIT1_INT_CLR (BIT(1))
+#define SLC_FRHOST_BIT0_INT_CLR (BIT(0))
+
+#define SLC_RX_STATUS                            (REG_SLC_BASE + 0x14)
+#define SLC_RX_EMPTY (BIT(1))
+#define SLC_RX_FULL (BIT(0))
+
+#define SLC_RX_FIFO_PUSH                          (REG_SLC_BASE + 0x18)
+#define SLC_RXFIFO_PUSH (BIT(16))
+#define SLC_RXFIFO_WDATA 0x000001FF
+#define SLC_RXFIFO_WDATA_S 0
+
+#define SLC_TX_STATUS                            (REG_SLC_BASE + 0x1C)
+#define SLC_TX_EMPTY (BIT(1))
+#define SLC_TX_FULL (BIT(0))
+
+#define SLC_TX_FIFO_POP                           (REG_SLC_BASE + 0x20)
+#define SLC_TXFIFO_POP (BIT(16))
+#define SLC_TXFIFO_RDATA 0x000007FF
+#define SLC_TXFIFO_RDATA_S 0
+
+#define SLC_RX_LINK                              (REG_SLC_BASE + 0x24)
+#define SLC_RXLINK_PARK (BIT(31))
+#define SLC_RXLINK_RESTART (BIT(30))
+#define SLC_RXLINK_START  (BIT(29))
+#define SLC_RXLINK_STOP  (BIT(28))
+#define SLC_RXLINK_DESCADDR_MASK 0x000FFFFF
+#define SLC_RXLINK_ADDR_S 0
+
+#define SLC_TX_LINK                              (REG_SLC_BASE + 0x28)
+#define SLC_TXLINK_PARK (BIT(31))
+#define SLC_TXLINK_RESTART (BIT(30))
+#define SLC_TXLINK_START  (BIT(29))
+#define SLC_TXLINK_STOP  (BIT(28))
+#define SLC_TXLINK_DESCADDR_MASK 0x000FFFFF
+#define SLC_TXLINK_ADDR_S 0
+
+#define SLC_INTVEC_TOHOST                        (REG_SLC_BASE + 0x2C)
+#define SLC_TOHOST_INTVEC 0x000000FF
+#define SLC_TOHOST_INTVEC_S 0
+
+#define SLC_TOKEN0                               (REG_SLC_BASE + 0x30)
+#define SLC_TOKEN0_MASK 0x00000FFF
+#define SLC_TOKEN0_S 16
+#define SLC_TOKEN0_LOCAL_INC_MORE (BIT(14))
+#define SLC_TOKEN0_LOCAL_INC (BIT(13))
+#define SLC_TOKEN0_LOCAL_WR (BIT(12))
+#define SLC_TOKEN0_LOCAL_WDATA_MASK 0x00000FFF
+#define SLC_TOKEN0_LOCAL_WDATA_S 0
+
+#define SLC_TOKEN1                               (REG_SLC_BASE + 0x34)
+#define SLC_TOKEN1_MASK 0x00000FFF
+#define SLC_TOKEN1_S 16
+#define SLC_TOKEN1_LOCAL_INC_MORE (BIT(14))
+#define SLC_TOKEN1_LOCAL_INC (BIT(13))
+#define SLC_TOKEN1_LOCAL_WR (BIT(12))
+#define SLC_TOKEN1_LOCAL_WDATA 0x00000FFF
+#define SLC_TOKEN1_LOCAL_WDATA_S 0
+
+#define SLC_CONF1                                (REG_SLC_BASE + 0x38)
+#define SLC_STATE0                               (REG_SLC_BASE + 0x3C)
+#define SLC_STATE1                               (REG_SLC_BASE + 0x40)
+
+#define SLC_BRIDGE_CONF                          (REG_SLC_BASE + 0x44)
+#ifndef ESP_MAC_5
+#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF
+#define SLC_TX_PUSH_IDLE_NUM_S 16
+#define SLC_TX_DUMMY_MODE (BIT(12))
+#endif
+#define SLC_FIFO_MAP_ENA 0x0000000F
+#define SLC_FIFO_MAP_ENA_S 8
+#define SLC_TXEOF_ENA  0x0000003F
+#define SLC_TXEOF_ENA_S 0
+
+#define SLC_RX_EOF_DES_ADDR                       (REG_SLC_BASE + 0x48)
+#define SLC_TX_EOF_DES_ADDR                       (REG_SLC_BASE + 0x4C)
+#define SLC_FROM_HOST_LAST_DESC                   SLC_TX_EOF_DES_ADDR
+#define SLC_TO_HOST_LAST_DESC                     SLC_RX_EOF_DES_ADDR
+
+#define SLC_RX_EOF_BFR_DES_ADDR                 (REG_SLC_BASE + 0x50)
+#define SLC_AHB_TEST                            (REG_SLC_BASE + 0x54)
+#define SLC_AHB_TESTADDR 0x00000003
+#define SLC_AHB_TESTADDR_S 4
+#define SLC_AHB_TESTMODE 0x00000007
+#define SLC_AHB_TESTMODE_S 0
+
+#define SLC_SDIO_ST                             (REG_SLC_BASE + 0x58)
+#define SLC_BUS_ST 0x00000007
+#define SLC_BUS_ST_S 12
+#define SLC_SDIO_WAKEUP (BIT(8))
+#define SLC_FUNC_ST 0x0000000F
+#define SLC_FUNC_ST_S 4
+#define SLC_CMD_ST 0x00000007
+#define SLC_CMD_ST_S 0
+
+#define SLC_RX_DSCR_CONF                        (REG_SLC_BASE + 0x5C)
+#ifdef ESP_MAC_5
+#define SLC_INFOR_NO_REPLACE (BIT(9))
+#define SLC_TOKEN_NO_REPLACE (BIT(8))
+#define SLC_POP_IDLE_CNT 0x000000FF
+#else
+#define SLC_RX_FILL_EN (BIT(20))
+#define SLC_RX_EOF_MODE (BIT(19))
+#define SLC_RX_FILL_MODE (BIT(18))
+#define SLC_INFOR_NO_REPLACE (BIT(17))
+#define SLC_TOKEN_NO_REPLACE (BIT(16))
+#define SLC_POP_IDLE_CNT 0x0000FFFF
+#endif
+#define SLC_POP_IDLE_CNT_S 0
+
+#define SLC_TXLINK_DSCR                         (REG_SLC_BASE + 0x60)
+#define SLC_TXLINK_DSCR_BF0                     (REG_SLC_BASE + 0x64)
+#define SLC_TXLINK_DSCR_BF1                     (REG_SLC_BASE + 0x68)
+#define SLC_RXLINK_DSCR                         (REG_SLC_BASE + 0x6C)
+#define SLC_RXLINK_DSCR_BF0                     (REG_SLC_BASE + 0x70)
+#define SLC_RXLINK_DSCR_BF1                     (REG_SLC_BASE + 0x74)
+#define SLC_DATE                                 (REG_SLC_BASE + 0x78)
+#define SLC_ID                                   (REG_SLC_BASE + 0x7C)
+
+#define SLC_HOST_CONF_W0                         (REG_SLC_BASE + 0x80 + 0x14)
+#define SLC_HOST_CONF_W1                         (REG_SLC_BASE + 0x80 + 0x18)
+#define SLC_HOST_CONF_W2                         (REG_SLC_BASE + 0x80 + 0x20)
+#define SLC_HOST_CONF_W3                         (REG_SLC_BASE + 0x80 + 0x24)
+#define SLC_HOST_CONF_W4                         (REG_SLC_BASE + 0x80 + 0x28)
+
+#define SLC_HOST_INTR_ST                         (REG_SLC_BASE + 0x80 + 0x1c)
+#define SLC_HOST_INTR_CLR                         (REG_SLC_BASE + 0x80 + 0x30)
+#define SLC_HOST_INTR_SOF_BIT                     (BIT(12))
+
+#define SLC_HOST_INTR_ENA                         (REG_SLC_BASE + 0x80 + 0x34)
+#define SLC_RX_NEW_PACKET_INT_ENA     (BIT23)
+#define SLC_HOST_TOHOST_BIT0_INT_ENA    (BIT0)
+#define SLC_HOST_CONF_W5                          (REG_SLC_BASE + 0x80 + 0x3C)
+#define SLC_HOST_INTR_RAW                         (REG_SLC_BASE + 0x80 + 0x8)
+#define SLC_HOST_INTR_ENA_BIT                      (BIT(23))
+//[15:12]: 0x3ff9xxxx -- 0b01  from_host
+//         0x3ffaxxxx -- 0b10  general
+//         0x3ffbxxxx -- 0b11  to_host
+#define SLC_DATA_ADDR_CLEAR_MASK                    (~(0xf<<12)) 
+#define SLC_FROM_HOST_ADDR_MASK                     (0x1<<12)
+#define SLC_TO_HOST_ADDR_MASK                       (0x3<<12)
+
+#define SLC_SET_FROM_HOST_ADDR_MASK(v)   do { \
+    (v) &= SLC_DATA_ADDR_CLEAR_MASK;  \
+    (v) |= SLC_FROM_HOST_ADDR_MASK;   \
+} while(0);
+
+#define SLC_SET_TO_HOST_ADDR_MASK(v)   do { \
+    (v) &= SLC_DATA_ADDR_CLEAR_MASK;  \
+    (v) |= SLC_TO_HOST_ADDR_MASK;   \
+} while(0);
+
+
+#define SLC_TX_DESC_DEBUG_REG  0x3ff0002c  //[15:0] set to 0xcccc
+
+#define SLC_INTEREST_EVENT (SLC_TX_EOF_INT_ENA | SLC_RX_EOF_INT_ENA | SLC_RX_UDF_INT_ENA | SLC_TX_DSCR_ERR_INT_ENA)
+#define TRIG_TOHOST_INT()  SET_PERI_REG_MASK(SLC_INTVEC_TOHOST , BIT0); CLEAR_PERI_REG_MASK(SLC_INTVEC_TOHOST , BIT0)
+
+
+#endif // SLC_REGISTER_H_INCLUDED