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Added memory fence to xt_rsil() (#6301)

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Without this the compiler may use memory references loaded to registers before the fence, in computation within the fence. These values could have changed before xt_rsil()
(critical section start) was called.
Note: this is needed to stop the compiler from reordering instructions at the critical section boundary.
This commit is contained in:
M Hightower 2019-07-14 12:36:39 -07:00 committed by Develo
parent 147fada3f5
commit 38d8b6efde
1 changed files with 1 additions and 1 deletions
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cores/esp8266/Arduino.h
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@ -159,7 +159,7 @@ void ets_intr_unlock();
// level 15 will disable ALL interrupts,
// level 0 will enable ALL interrupts,
//
#define xt_rsil(level) (__extension__({uint32_t state; __asm__ __volatile__("rsil %0," __STRINGIFY(level) : "=a" (state)); state;}))
#define xt_rsil(level) (__extension__({uint32_t state; __asm__ __volatile__("rsil %0," __STRINGIFY(level) : "=a" (state) :: "memory"); state;}))
#define xt_wsr_ps(state) __asm__ __volatile__("wsr %0,ps; isync" :: "a" (state) : "memory")
#define interrupts() xt_rsil(0)