mirror of
https://github.com/esp8266/Arduino.git
synced 2025-04-25 20:02:37 +03:00
small clean up of HardwareSerial
This commit is contained in:
parent
ec8110b78c
commit
34b09f7e23
@ -41,6 +41,20 @@ extern "C" {
|
||||
|
||||
#define UART_TX_FIFO_SIZE 0x80
|
||||
|
||||
struct uart_ {
|
||||
int uart_nr;
|
||||
int baud_rate;
|
||||
bool rxEnabled;
|
||||
bool txEnabled;
|
||||
uint8_t rxPin;
|
||||
uint8_t txPin;
|
||||
};
|
||||
|
||||
static const int UART0 = 0;
|
||||
static const int UART1 = 1;
|
||||
static const int UART_NO = -1;
|
||||
|
||||
|
||||
/**
|
||||
* UART GPIOs
|
||||
*
|
||||
@ -86,7 +100,7 @@ void uart_disarm_tx_interrupt(uart_t* uart);
|
||||
void uart_set_baudrate(uart_t* uart, int baud_rate);
|
||||
int uart_get_baudrate(uart_t* uart);
|
||||
|
||||
uart_t* uart_init(UARTnr_t uart_nr, int baudrate, byte config);
|
||||
uart_t* uart_init(int uart_nr, int baudrate, byte config);
|
||||
void uart_uninit(uart_t* uart);
|
||||
void uart_swap(uart_t* uart);
|
||||
|
||||
@ -94,8 +108,8 @@ void uart_ignore_char(char c);
|
||||
void uart0_write_char(char c);
|
||||
void uart1_write_char(char c);
|
||||
|
||||
void uart_set_debug(UARTnr_t uart_nr);
|
||||
UARTnr_t uart_get_debug();
|
||||
void uart_set_debug(int uart_nr);
|
||||
int uart_get_debug();
|
||||
|
||||
// ####################################################################################################
|
||||
// ####################################################################################################
|
||||
@ -108,12 +122,12 @@ void ICACHE_RAM_ATTR uart_interrupt_handler(uart_t* uart) {
|
||||
if(Serial.isRxEnabled()) {
|
||||
if(status & (1 << UIFF)) {
|
||||
while(true) {
|
||||
int rx_count = (U0S >> USTXC) & 0xFF;
|
||||
int rx_count = (U0S >> USTXC) & 0xff;
|
||||
if(!rx_count)
|
||||
break;
|
||||
|
||||
while(rx_count--) {
|
||||
char c = U0F & 0xFF;
|
||||
char c = U0F & 0xff;
|
||||
Serial._rx_complete_irq(c);
|
||||
}
|
||||
}
|
||||
@ -133,12 +147,12 @@ void ICACHE_RAM_ATTR uart_interrupt_handler(uart_t* uart) {
|
||||
if(Serial1.isRxEnabled()) {
|
||||
if(status & (1 << UIFF)) {
|
||||
while(true) {
|
||||
int rx_count = (U1S >> USTXC) & 0xFF;
|
||||
int rx_count = (U1S >> USTXC) & 0xff;
|
||||
if(!rx_count)
|
||||
break;
|
||||
|
||||
while(rx_count--) {
|
||||
char c = U1F & 0xFF;
|
||||
char c = U1F & 0xff;
|
||||
Serial1._rx_complete_irq(c);
|
||||
}
|
||||
}
|
||||
@ -156,28 +170,28 @@ void ICACHE_RAM_ATTR uart_interrupt_handler(uart_t* uart) {
|
||||
|
||||
// ####################################################################################################
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_wait_for_tx_fifo(uart_t* uart, size_t size_needed) {
|
||||
void uart_wait_for_tx_fifo(uart_t* uart, size_t size_needed) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
if(uart->txEnabled) {
|
||||
while(true) {
|
||||
size_t tx_count = (USS(uart->uart_nr) >> USTXC) & 0xFF;
|
||||
size_t tx_count = (USS(uart->uart_nr) >> USTXC) & 0xff;
|
||||
if(tx_count <= (UART_TX_FIFO_SIZE - size_needed))
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
size_t ICACHE_FLASH_ATTR uart_get_tx_fifo_room(uart_t* uart) {
|
||||
size_t uart_get_tx_fifo_room(uart_t* uart) {
|
||||
if(uart == 0)
|
||||
return 0;
|
||||
if(uart->txEnabled) {
|
||||
return UART_TX_FIFO_SIZE - ((USS(uart->uart_nr) >> USTXC) & 0xFF);
|
||||
return UART_TX_FIFO_SIZE - ((USS(uart->uart_nr) >> USTXC) & 0xff);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_wait_for_transmit(uart_t* uart) {
|
||||
void uart_wait_for_transmit(uart_t* uart) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
if(uart->txEnabled) {
|
||||
@ -185,7 +199,7 @@ void ICACHE_FLASH_ATTR uart_wait_for_transmit(uart_t* uart) {
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_transmit_char(uart_t* uart, char c) {
|
||||
void uart_transmit_char(uart_t* uart, char c) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
if(uart->txEnabled) {
|
||||
@ -193,7 +207,7 @@ void ICACHE_FLASH_ATTR uart_transmit_char(uart_t* uart, char c) {
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_transmit(uart_t* uart, const char* buf, size_t size) {
|
||||
void uart_transmit(uart_t* uart, const char* buf, size_t size) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
if(uart->txEnabled) {
|
||||
@ -208,7 +222,7 @@ void ICACHE_FLASH_ATTR uart_transmit(uart_t* uart, const char* buf, size_t size)
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_flush(uart_t* uart) {
|
||||
void uart_flush(uart_t* uart) {
|
||||
uint32_t tmp = 0x00000000;
|
||||
|
||||
if(uart == 0)
|
||||
@ -226,7 +240,7 @@ void ICACHE_FLASH_ATTR uart_flush(uart_t* uart) {
|
||||
USC0(uart->uart_nr) &= ~(tmp);
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_interrupt_enable(uart_t* uart) {
|
||||
void uart_interrupt_enable(uart_t* uart) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
USIC(uart->uart_nr) = 0x1ff;
|
||||
@ -237,7 +251,7 @@ void ICACHE_FLASH_ATTR uart_interrupt_enable(uart_t* uart) {
|
||||
ETS_UART_INTR_ENABLE();
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_interrupt_disable(uart_t* uart) {
|
||||
void uart_interrupt_disable(uart_t* uart) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
if(uart->rxEnabled) {
|
||||
@ -249,7 +263,7 @@ void ICACHE_FLASH_ATTR uart_interrupt_disable(uart_t* uart) {
|
||||
//ETS_UART_INTR_DISABLE(); // never disable irq complete may its needed by the other Serial Interface!
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_arm_tx_interrupt(uart_t* uart) {
|
||||
void uart_arm_tx_interrupt(uart_t* uart) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
if(uart->txEnabled) {
|
||||
@ -257,7 +271,7 @@ void ICACHE_FLASH_ATTR uart_arm_tx_interrupt(uart_t* uart) {
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_disarm_tx_interrupt(uart_t* uart) {
|
||||
void uart_disarm_tx_interrupt(uart_t* uart) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
if(uart->txEnabled) {
|
||||
@ -265,20 +279,20 @@ void ICACHE_FLASH_ATTR uart_disarm_tx_interrupt(uart_t* uart) {
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_set_baudrate(uart_t* uart, int baud_rate) {
|
||||
void uart_set_baudrate(uart_t* uart, int baud_rate) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
uart->baud_rate = baud_rate;
|
||||
USD(uart->uart_nr) = (80000000UL / uart->baud_rate);
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR uart_get_baudrate(uart_t* uart) {
|
||||
int uart_get_baudrate(uart_t* uart) {
|
||||
if(uart == 0)
|
||||
return 0;
|
||||
return uart->baud_rate;
|
||||
}
|
||||
|
||||
uart_t* ICACHE_FLASH_ATTR uart_init(UARTnr_t uart_nr, int baudrate, byte config) {
|
||||
uart_t* uart_init(int uart_nr, int baudrate, byte config) {
|
||||
|
||||
uint32_t conf1 = 0x00000000;
|
||||
uart_t* uart = (uart_t*) os_malloc(sizeof(uart_t));
|
||||
@ -329,7 +343,7 @@ uart_t* ICACHE_FLASH_ATTR uart_init(UARTnr_t uart_nr, int baudrate, byte config)
|
||||
return uart;
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_uninit(uart_t* uart) {
|
||||
void uart_uninit(uart_t* uart) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
uart_interrupt_disable(uart);
|
||||
@ -358,7 +372,7 @@ void ICACHE_FLASH_ATTR uart_uninit(uart_t* uart) {
|
||||
os_free(uart);
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_swap(uart_t* uart) {
|
||||
void uart_swap(uart_t* uart) {
|
||||
if(uart == 0)
|
||||
return;
|
||||
switch(uart->uart_nr) {
|
||||
@ -394,10 +408,10 @@ void ICACHE_FLASH_ATTR uart_swap(uart_t* uart) {
|
||||
// ####################################################################################################
|
||||
// ####################################################################################################
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_ignore_char(char c) {
|
||||
void uart_ignore_char(char c) {
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart0_write_char(char c) {
|
||||
void uart0_write_char(char c) {
|
||||
if(&Serial != NULL && Serial.isTxEnabled()) {
|
||||
if(c == '\n') {
|
||||
Serial.write('\r');
|
||||
@ -411,7 +425,7 @@ void ICACHE_FLASH_ATTR uart0_write_char(char c) {
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart1_write_char(char c) {
|
||||
void uart1_write_char(char c) {
|
||||
if(&Serial1 != NULL && Serial1.isTxEnabled()) {
|
||||
if(c == '\n') {
|
||||
Serial1.write('\r');
|
||||
@ -425,8 +439,9 @@ void ICACHE_FLASH_ATTR uart1_write_char(char c) {
|
||||
}
|
||||
}
|
||||
|
||||
static UARTnr_t s_uart_debug_nr = UART0;
|
||||
void ICACHE_FLASH_ATTR uart_set_debug(UARTnr_t uart_nr) {
|
||||
static int s_uart_debug_nr = UART0;
|
||||
|
||||
void uart_set_debug(int uart_nr) {
|
||||
s_uart_debug_nr = uart_nr;
|
||||
switch(s_uart_debug_nr) {
|
||||
case UART0:
|
||||
@ -445,7 +460,7 @@ void ICACHE_FLASH_ATTR uart_set_debug(UARTnr_t uart_nr) {
|
||||
}
|
||||
}
|
||||
|
||||
UARTnr_t ICACHE_FLASH_ATTR uart_get_debug() {
|
||||
int uart_get_debug() {
|
||||
return s_uart_debug_nr;
|
||||
}
|
||||
|
||||
@ -453,12 +468,11 @@ UARTnr_t ICACHE_FLASH_ATTR uart_get_debug() {
|
||||
// ####################################################################################################
|
||||
// ####################################################################################################
|
||||
|
||||
ICACHE_FLASH_ATTR HardwareSerial::HardwareSerial(UARTnr_t uart_nr) :
|
||||
_uart(0), _tx_buffer(0), _rx_buffer(0), _written(false) {
|
||||
_uart_nr = uart_nr;
|
||||
HardwareSerial::HardwareSerial(int uart_nr) :
|
||||
_uart_nr(uart_nr), _uart(0), _tx_buffer(0), _rx_buffer(0), _written(false) {
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::begin(unsigned long baud, byte config) {
|
||||
void HardwareSerial::begin(unsigned long baud, byte config) {
|
||||
|
||||
// disable debug for this interface
|
||||
if(uart_get_debug() == _uart_nr) {
|
||||
@ -472,16 +486,18 @@ void ICACHE_FLASH_ATTR HardwareSerial::begin(unsigned long baud, byte config) {
|
||||
}
|
||||
|
||||
if(_uart->rxEnabled) {
|
||||
_rx_buffer = new cbuf(SERIAL_RX_BUFFER_SIZE);
|
||||
if (!_rx_buffer)
|
||||
_rx_buffer = new cbuf(SERIAL_RX_BUFFER_SIZE);
|
||||
}
|
||||
if(_uart->txEnabled) {
|
||||
_tx_buffer = new cbuf(SERIAL_TX_BUFFER_SIZE);
|
||||
if (!_tx_buffer)
|
||||
_tx_buffer = new cbuf(SERIAL_TX_BUFFER_SIZE);
|
||||
}
|
||||
_written = false;
|
||||
delay(1);
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::end() {
|
||||
void HardwareSerial::end() {
|
||||
if(uart_get_debug() == _uart_nr) {
|
||||
uart_set_debug(UART_NO);
|
||||
}
|
||||
@ -493,13 +509,13 @@ void ICACHE_FLASH_ATTR HardwareSerial::end() {
|
||||
_tx_buffer = 0;
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::swap() {
|
||||
void HardwareSerial::swap() {
|
||||
if(_uart == 0)
|
||||
return;
|
||||
uart_swap(_uart);
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::setDebugOutput(bool en) {
|
||||
void HardwareSerial::setDebugOutput(bool en) {
|
||||
if(_uart == 0)
|
||||
return;
|
||||
if(en) {
|
||||
@ -512,19 +528,19 @@ void ICACHE_FLASH_ATTR HardwareSerial::setDebugOutput(bool en) {
|
||||
}
|
||||
}
|
||||
|
||||
bool ICACHE_FLASH_ATTR HardwareSerial::isTxEnabled(void) {
|
||||
bool HardwareSerial::isTxEnabled(void) {
|
||||
if(_uart == 0)
|
||||
return false;
|
||||
return _uart->txEnabled;
|
||||
}
|
||||
|
||||
bool ICACHE_FLASH_ATTR HardwareSerial::isRxEnabled(void) {
|
||||
bool HardwareSerial::isRxEnabled(void) {
|
||||
if(_uart == 0)
|
||||
return false;
|
||||
return _uart->rxEnabled;
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::available(void) {
|
||||
int HardwareSerial::available(void) {
|
||||
if(_uart == 0)
|
||||
return 0;
|
||||
if(_uart->rxEnabled) {
|
||||
@ -534,7 +550,7 @@ int ICACHE_FLASH_ATTR HardwareSerial::available(void) {
|
||||
}
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::peek(void) {
|
||||
int HardwareSerial::peek(void) {
|
||||
if(_uart == 0)
|
||||
return -1;
|
||||
if(_uart->rxEnabled) {
|
||||
@ -544,7 +560,7 @@ int ICACHE_FLASH_ATTR HardwareSerial::peek(void) {
|
||||
}
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::read(void) {
|
||||
int HardwareSerial::read(void) {
|
||||
if(_uart == 0)
|
||||
return -1;
|
||||
if(_uart->rxEnabled) {
|
||||
@ -554,7 +570,7 @@ int ICACHE_FLASH_ATTR HardwareSerial::read(void) {
|
||||
}
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::availableForWrite(void) {
|
||||
int HardwareSerial::availableForWrite(void) {
|
||||
if(_uart == 0)
|
||||
return 0;
|
||||
if(_uart->txEnabled) {
|
||||
@ -564,7 +580,7 @@ int ICACHE_FLASH_ATTR HardwareSerial::availableForWrite(void) {
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::flush() {
|
||||
void HardwareSerial::flush() {
|
||||
if(_uart == 0)
|
||||
return;
|
||||
if(!_uart->txEnabled)
|
||||
@ -578,7 +594,7 @@ void ICACHE_FLASH_ATTR HardwareSerial::flush() {
|
||||
_written = false;
|
||||
}
|
||||
|
||||
size_t ICACHE_FLASH_ATTR HardwareSerial::write(uint8_t c) {
|
||||
size_t HardwareSerial::write(uint8_t c) {
|
||||
if(_uart == 0 || !_uart->txEnabled)
|
||||
return 0;
|
||||
_written = true;
|
||||
@ -599,17 +615,17 @@ size_t ICACHE_FLASH_ATTR HardwareSerial::write(uint8_t c) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
ICACHE_FLASH_ATTR HardwareSerial::operator bool() const {
|
||||
HardwareSerial::operator bool() const {
|
||||
return _uart != 0;
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::_rx_complete_irq(char c) {
|
||||
void HardwareSerial::_rx_complete_irq(char c) {
|
||||
if(_rx_buffer) {
|
||||
_rx_buffer->write(c);
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::_tx_empty_irq(void) {
|
||||
void HardwareSerial::_tx_empty_irq(void) {
|
||||
if(_uart == 0)
|
||||
return;
|
||||
if(_tx_buffer == 0)
|
||||
|
@ -62,29 +62,19 @@
|
||||
|
||||
class cbuf;
|
||||
|
||||
typedef enum {
|
||||
UART0 = 0, UART1 = 1, UART_NO = 0xFF
|
||||
} UARTnr_t;
|
||||
|
||||
typedef struct {
|
||||
UARTnr_t uart_nr;
|
||||
int baud_rate;
|
||||
bool rxEnabled;
|
||||
bool txEnabled;
|
||||
uint8_t rxPin;
|
||||
uint8_t txPin;
|
||||
} uart_t;
|
||||
struct uart_;
|
||||
typedef struct uart_ uart_t;
|
||||
|
||||
class HardwareSerial: public Stream {
|
||||
public:
|
||||
HardwareSerial(UARTnr_t uart_nr);
|
||||
HardwareSerial(int uart_nr);
|
||||
|
||||
void begin(unsigned long baud) {
|
||||
begin(baud, SERIAL_8N1);
|
||||
}
|
||||
void begin(unsigned long, uint8_t);
|
||||
void end();
|
||||
void swap(); //use GPIO13 and GPIO15 as RX and TX
|
||||
void swap(); //toggle between use of GPIO13/GPIO15 or GPIO3/GPIO1 as RX and TX
|
||||
int available(void) override;
|
||||
int peek(void) override;
|
||||
int read(void) override;
|
||||
@ -116,7 +106,7 @@ class HardwareSerial: public Stream {
|
||||
void _tx_empty_irq(void);
|
||||
|
||||
protected:
|
||||
UARTnr_t _uart_nr;
|
||||
int _uart_nr;
|
||||
uart_t* _uart;
|
||||
cbuf* _tx_buffer;
|
||||
cbuf* _rx_buffer;
|
||||
|
Loading…
x
Reference in New Issue
Block a user