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mirror of https://github.com/esp8266/Arduino.git synced 2026-10-23 19:08:55 +03:00

ENC28J60: add missing end() required by LwipIntfDev (#9323)

LwipIntfDev<RawDev> calls RawDev::end() from LwipIntfDev::end() and from the two
error paths of LwipIntfDev::begin(). Wiznet5500 provides end(), ENC28J60 does
not, so LwipIntfDev<ENC28J60> - i.e. ENC28J60lwIP - no longer compiles:

  LwipIntfDev.h:280:20: error: 'end' is not a member of 'ENC28J60'
  LwipIntfDev.h:294:24: error: 'end' is not a member of 'ENC28J60'

The calls came in with #9023, which only touched cores/esp8266/LwipIntfDev.h.

Wiznet5500::end() closes socket 0 and leaves the chip powered and configured,
since a following begin() resets and reopens it anyway. The ENC28J60 equivalent
of closing the socket is clearing ECON1.RXEN, the bit that reset() sets last to
enable reception. ECON1 is mapped into every bank, so no bank switch is needed,
and no frame can be in flight because sendFrame() polls ECON1.TXRTS until the
frame has left.
This commit is contained in:
Claas Flint
2026-08-27 13:20:56 +02:00
committed by GitHub
parent f946290ea9
commit 1475ed7d49
2 changed files with 14 additions and 0 deletions

View File

@@ -546,6 +546,14 @@ boolean ENC28J60::begin(const uint8_t* address)
/*---------------------------------------------------------------------------*/
void ENC28J60::end()
{
// stop reception. ECON1 is mirrored into every bank, so no bank switch is needed
clearregbitfield(ECON1, ECON1_RXEN);
}
/*---------------------------------------------------------------------------*/
uint16_t ENC28J60::sendFrame(const uint8_t* data, uint16_t datalen)
{
uint16_t dataend;

View File

@@ -62,6 +62,12 @@ public:
*/
boolean begin(const uint8_t* address);
/**
Shut down the Ethernet controller
Stops the reception of Ethernet frames until the next ::begin()
*/
void end();
/**
Send an Ethernet frame
@param data a pointer to the data to send