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[ARC32] add missing includes

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Martino Facchin 2016-12-06 18:42:55 +01:00
parent 3e4915e8c9
commit 5175ae9fd2
6 changed files with 3779 additions and 0 deletions
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89
src/include/arc32/power_states.h Normal file
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/*
* Copyright (c) 2016, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __POWER_STATES_H__
#define __POWER_STATES_H__
/**
* SoC Power mode control for Quark SE Microcontrollers.
*
* Available SoC states are:
* - Low Power Sensing Standby (LPSS)
* - Sleep
*
* LPSS can only be enabled from the Sensor core,
* refer to @ref ss_power_soc_lpss_enable for further details.
*
* @defgroup groupSoCPower Quark SE SoC Power states
* @{
*/
/**
* Enter SoC sleep state.
*
* Put the SoC into sleep state until next SoC wake event.
*
* - Core well is turned off
* - Always on well is on
* - Hybrid Clock is off
* - RTC Clock is on
*
* Possible SoC wake events are:
* - Low Power Comparator Interrupt
* - AON GPIO Interrupt
* - AON Timer Interrupt
* - RTC Interrupt
*/
void power_soc_sleep(void);
/**
* Enter SoC deep sleep state.
*
* Put the SoC into deep sleep state until next SoC wake event.
*
* - Core well is turned off
* - Always on well is on
* - Hybrid Clock is off
* - RTC Clock is on
*
* Possible SoC wake events are:
* - Low Power Comparator Interrupt
* - AON GPIO Interrupt
* - AON Timer Interrupt
* - RTC Interrupt
*
* This function puts 1P8V regulators and 3P3V into Linear Mode.
*/
void power_soc_deep_sleep(void);
/**
* @}
*/
#endif /* __POWER_STATES_H__ */

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src/include/arc32/qm_interrupt_router_regs.h Normal file
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/*
* Copyright (c) 2016, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __QM_INTERRUPT_ROUTER_REGS_H__
#define __QM_INTERRUPT_ROUTER_REGS_H__
/**
* Quark SE SoC Event Router registers.
*
* @defgroup groupQUARKSESEEVENTROUTER SoC Event Router (SE)
* @{
*/
/**
* Masks for single source interrupts in the Event Router.
* To enable: reg &= ~(MASK)
* To disable: reg |= MASK;
*/
#define QM_IR_INT_LMT_MASK BIT(0)
#define QM_IR_INT_SS_MASK BIT(8)
/* Masks for single source halts in the Event Router. */
#define QM_IR_INT_LMT_HALT_MASK BIT(16)
#define QM_IR_INT_SS_HALT_MASK BIT(24)
/* Event Router Unmask interrupts for a peripheral. */
#define QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_) \
(_peripheral_ &= ~(QM_IR_INT_LMT_MASK))
#define QM_IR_UNMASK_SS_INTERRUPTS(_peripheral_) \
(_peripheral_ &= ~(QM_IR_INT_SS_MASK))
/* Mask interrupts for a peripheral. */
#define QM_IR_MASK_LMT_INTERRUPTS(_peripheral_) \
(_peripheral_ |= QM_IR_INT_LMT_MASK)
#define QM_IR_MASK_SS_INTERRUPTS(_peripheral_) \
(_peripheral_ |= QM_IR_INT_SS_MASK)
/* Unmask halt for a peripheral. */
#define QM_IR_UNMASK_LMT_HALTS(_peripheral_) \
(_peripheral_ &= ~(QM_IR_INT_LMT_HALT_MASK))
#define QM_IR_UNMASK_SS_HALTS(_peripheral_) \
(_peripheral_ &= ~(QM_IR_INT_SS_HALT_MASK))
/* Mask halt for a peripheral. */
#define QM_IR_MASK_LMT_HALTS(_peripheral_) \
(_peripheral_ |= QM_IR_INT_LMT_HALT_MASK)
#define QM_IR_MASK_SS_HALTS(_peripheral_) \
(_peripheral_ |= QM_IR_INT_SS_HALT_MASK)
#define QM_IR_GET_LMT_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_LMT_MASK)
#define QM_IR_GET_LMT_HALT_MASK(_peripheral_) \
(_peripheral_ & QM_IR_INT_LMT_HALT_MASK)
#define QM_IR_GET_SS_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_SS_MASK)
#define QM_IR_GET_SS_HALT_MASK(_peripheral_) \
(_peripheral_ & QM_IR_INT_SS_HALT_MASK)
/* Define macros for use by the active core. */
#if (QM_LAKEMONT)
#define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_)
#define QM_IR_MASK_INTERRUPTS(_peripheral_) \
QM_IR_MASK_LMT_INTERRUPTS(_peripheral_)
#define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_LMT_HALTS(_peripheral_)
#define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_LMT_HALTS(_peripheral_)
#define QM_IR_INT_MASK QM_IR_INT_LMT_MASK
#define QM_IR_INT_HALT_MASK QM_IR_INT_LMT_HALT_MASK
#define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_LMT_MASK(_peripheral_)
#define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_LMT_HALT_MASK(_peripheral_)
#elif(QM_SENSOR)
#define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
QM_IR_UNMASK_SS_INTERRUPTS(_peripheral_)
#define QM_IR_MASK_INTERRUPTS(_peripheral_) \
QM_IR_MASK_SS_INTERRUPTS(_peripheral_)
#define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_SS_HALTS(_peripheral_)
#define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_SS_HALTS(_peripheral_)
#define QM_IR_INT_MASK QM_IR_INT_SS_MASK
#define QM_IR_INT_HALT_MASK QM_IR_INT_SS_HALT_MASK
#define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_SS_MASK(_peripheral_)
#define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_SS_HALT_MASK(_peripheral_)
#else
#error "No active core selected."
#endif
/** SS I2C Interrupt register map. */
typedef struct {
QM_RW uint32_t err_mask;
QM_RW uint32_t rx_avail_mask;
QM_RW uint32_t tx_req_mask;
QM_RW uint32_t stop_det_mask;
} int_ss_i2c_reg_t;
/** SS SPI Interrupt register map. */
typedef struct {
QM_RW uint32_t err_int_mask;
QM_RW uint32_t rx_avail_mask;
QM_RW uint32_t tx_req_mask;
} int_ss_spi_reg_t;
/** Interrupt register map. */
typedef struct {
QM_RW uint32_t ss_adc_0_error_int_mask; /**< Sensor ADC 0 Error. */
QM_RW uint32_t ss_adc_0_int_mask; /**< Sensor ADC 0. */
QM_RW uint32_t ss_gpio_0_int_mask; /**< Sensor GPIO 0. */
QM_RW uint32_t ss_gpio_1_int_mask; /**< Sensor GPIO 1. */
int_ss_i2c_reg_t ss_i2c_0_int; /**< Sensor I2C 0 Masks. */
int_ss_i2c_reg_t ss_i2c_1_int; /**< Sensor I2C 1 Masks. */
int_ss_spi_reg_t ss_spi_0_int; /**< Sensor SPI 0 Masks. */
int_ss_spi_reg_t ss_spi_1_int; /**< Sensor SPI 1 Masks. */
QM_RW uint32_t i2c_master_0_int_mask; /**< I2C Master 0. */
QM_RW uint32_t i2c_master_1_int_mask; /**< I2C Master 1. */
QM_R uint32_t reserved;
QM_RW uint32_t spi_master_0_int_mask; /**< SPI Master 0. */
QM_RW uint32_t spi_master_1_int_mask; /**< SPI Master 1. */
QM_RW uint32_t spi_slave_0_int_mask; /**< SPI Slave 0. */
QM_RW uint32_t uart_0_int_mask; /**< UART 0. */
QM_RW uint32_t uart_1_int_mask; /**< UART 1. */
QM_RW uint32_t i2s_0_int_mask; /**< I2S 0. */
QM_RW uint32_t gpio_0_int_mask; /**< GPIO 0. */
QM_RW uint32_t pwm_0_int_mask; /**< PWM 0. */
QM_RW uint32_t usb_0_int_mask; /**< USB 0. */
QM_RW uint32_t rtc_0_int_mask; /**< RTC 0. */
QM_RW uint32_t wdt_0_int_mask; /**< WDT 0. */
QM_RW uint32_t dma_0_int_0_mask; /**< DMA 0 Ch 0. */
QM_RW uint32_t dma_0_int_1_mask; /**< DMA 0 Ch 1. */
QM_RW uint32_t dma_0_int_2_mask; /**< DMA 0 Ch 2. */
QM_RW uint32_t dma_0_int_3_mask; /**< DMA 0 Ch 3. */
QM_RW uint32_t dma_0_int_4_mask; /**< DMA 0 Ch 4. */
QM_RW uint32_t dma_0_int_5_mask; /**< DMA 0 Ch 5. */
QM_RW uint32_t dma_0_int_6_mask; /**< DMA 0 Ch 6. */
QM_RW uint32_t dma_0_int_7_mask; /**< DMA 0 Ch 7. */
/** Mailbox 0 Combined 8 Channel Host and Sensor Masks. */
QM_RW uint32_t mailbox_0_int_mask;
/** Comparator Sensor Halt Mask. */
QM_RW uint32_t comparator_0_ss_halt_int_mask;
/** Comparator Host Halt Mask. */
QM_RW uint32_t comparator_0_host_halt_int_mask;
/** Comparator Sensor Mask. */
QM_RW uint32_t comparator_0_ss_int_mask;
/** Comparator Host Mask. */
QM_RW uint32_t comparator_0_host_int_mask;
QM_RW uint32_t host_bus_error_int_mask; /**< Host bus error. */
QM_RW uint32_t dma_0_error_int_mask; /**< DMA 0 Error. */
QM_RW uint32_t sram_mpr_0_int_mask; /**< SRAM MPR 0. */
QM_RW uint32_t flash_mpr_0_int_mask; /**< Flash MPR 0. */
QM_RW uint32_t flash_mpr_1_int_mask; /**< Flash MPR 1. */
QM_RW uint32_t aonpt_0_int_mask; /**< AONPT 0. */
QM_RW uint32_t adc_0_pwr_int_mask; /**< ADC 0 PWR. */
QM_RW uint32_t adc_0_cal_int_mask; /**< ADC 0 CAL. */
QM_RW uint32_t aon_gpio_0_int_mask; /**< AON GPIO 0. */
QM_RW uint32_t lock_int_mask_reg; /**< Interrupt Mask Lock Register. */
} qm_interrupt_router_reg_t;
/* Number of SCSS interrupt mask registers (excluding mask lock register). */
#define QM_INTERRUPT_ROUTER_MASK_NUMREG \
((sizeof(qm_interrupt_router_reg_t) / sizeof(uint32_t)) - 1)
/* Default POR SCSS interrupt mask (all interrupts masked). */
#define QM_INTERRUPT_ROUTER_MASK_DEFAULT (0xFFFFFFFF)
#if (UNIT_TEST)
qm_interrupt_router_reg_t test_interrupt_router;
#define QM_INTERRUPT_ROUTER \
((qm_interrupt_router_reg_t *)(&test_interrupt_router))
#else
/* System control subsystem interrupt masking register block. */
#define QM_INTERRUPT_ROUTER_BASE (0xB0800400)
#define QM_INTERRUPT_ROUTER \
((qm_interrupt_router_reg_t *)QM_INTERRUPT_ROUTER_BASE)
#endif
#define QM_IR_DMA_ERROR_HOST_MASK (0x000000FF)
#define QM_IR_DMA_ERROR_SS_MASK (0x0000FF00)
/** @} */
#endif /* __QM_INTERRUPT_ROUTER_REGS_H__ */

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src/include/arc32/qm_sensor_regs.h Normal file
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/*
* Copyright (c) 2016, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SENSOR_REGISTERS_H__
#define __SENSOR_REGISTERS_H__
/**
* Quark SE SoC Sensor Subsystem Registers.
*
* For detailed description please read the SOC datasheet.
*
* @defgroup groupSSSEREG SoC Registers (Sensor Subsystem)
* @{
*/
#define BIT(x) (1U << (x))
/* Bitwise OR operation macro for registers in the auxiliary memory space. */
#define QM_SS_REG_AUX_OR(reg, mask) \
(__builtin_arc_sr(__builtin_arc_lr(reg) | (mask), reg))
/* Bitwise NAND operation macro for registers in the auxiliary memory space. */
#define QM_SS_REG_AUX_NAND(reg, mask) \
(__builtin_arc_sr(__builtin_arc_lr(reg) & (~(mask)), reg))
/* Sensor Subsystem status32 register. */
#define QM_SS_AUX_STATUS32 (0xA)
/** Interrupt priority threshold. */
#define QM_SS_STATUS32_E_MASK (0x1E)
/** Interrupt enable. */
#define QM_SS_STATUS32_IE_MASK BIT(31)
/* Sensor Subsystem control register. */
#define QM_SS_AUX_IC_CTRL (0x11)
/* Sensor Subsystem cache invalidate register. */
#define QM_SS_AUX_IC_IVIL (0x19)
/* Sensor Subsystem vector base register. */
#define QM_SS_AUX_INT_VECTOR_BASE (0x25)
/**
* @name SS Interrupt
* @{
*/
#define QM_SS_EXCEPTION_NUM (16) /* Exceptions and traps in ARC EM core. */
#define QM_SS_INT_TIMER_NUM (2) /* Internal interrupts in ARC EM core. */
#define QM_SS_IRQ_SENSOR_NUM (18) /* IRQ's from the Sensor Subsystem. */
#define QM_SS_IRQ_COMMON_NUM (32) /* IRQ's from the common SoC fabric. */
#define QM_SS_INT_VECTOR_NUM \
(QM_SS_EXCEPTION_NUM + QM_SS_INT_TIMER_NUM + QM_SS_IRQ_SENSOR_NUM + \
QM_SS_IRQ_COMMON_NUM)
#define QM_SS_IRQ_NUM (QM_SS_IRQ_SENSOR_NUM + QM_SS_IRQ_COMMON_NUM)
/**
* SS IRQ context type.
*
* Applications should not modify the content.
* This structure is only intended to be used by
* qm_irq_save_context and qm_irq_restore_context functions.
*/
typedef struct {
uint32_t status32_irq_threshold; /**< STATUS32 Interrupt Threshold. */
uint32_t status32_irq_enable; /**< STATUS32 Interrupt Enable. */
uint32_t irq_ctrl; /**< Interrupt Context Saving Control Register. */
/**
* IRQ configuration:
* - IRQ Priority:BIT(6):BIT(2)
* - IRQ Trigger:BIT(1)
* - IRQ Enable:BIT(0)
*/
uint8_t irq_config[QM_SS_INT_VECTOR_NUM - 1];
} qm_irq_context_t;
/** General Purpose register map. */
typedef struct {
volatile uint32_t gps0; /**< General Purpose Sticky Register 0 */
volatile uint32_t gps1; /**< General Purpose Sticky Register 1 */
volatile uint32_t gps2; /**< General Purpose Sticky Register 2 */
volatile uint32_t gps3; /**< General Purpose Sticky Register 3 */
volatile uint32_t reserved;
volatile uint32_t gp0; /**< General Purpose Scratchpad Register 0 */
volatile uint32_t gp1; /**< General Purpose Scratchpad Register 1 */
volatile uint32_t gp2; /**< General Purpose Scratchpad Register 2 */
volatile uint32_t gp3; /**< General Purpose Scratchpad Register 3 */
volatile uint32_t reserved1;
volatile uint32_t id; /**< Identification Register */
volatile uint32_t rev; /**< Revision Register */
volatile uint32_t wo_sp; /**< Write-One-to-Set Scratchpad Register */
volatile uint32_t
wo_st; /**< Write-One-to-Set Sticky Scratchpad Register */
} qm_scss_gp_reg_t;
#define QM_SCSS_GP_BASE (0xB0800100)
#define QM_SCSS_GP ((qm_scss_gp_reg_t *)QM_SCSS_GP_BASE)
/* The GPS0 register usage. */
#define QM_GPS0_BIT_FM (0) /**< Start Firmware Manager. */
#define QM_GPS0_BIT_X86_WAKEUP (1) /**< Lakemont core reset type. */
#define QM_GPS0_BIT_SENSOR_WAKEUP (2) /**< Sensor core reset type. */
/** System Core register map. */
typedef struct {
volatile uint32_t osc0_cfg0; /**< Hybrid Oscillator Configuration 0. */
volatile uint32_t osc0_stat1; /**< Hybrid Oscillator status 1. */
volatile uint32_t osc0_cfg1; /**< Hybrid Oscillator configuration 1. */
volatile uint32_t osc1_stat0; /**< RTC Oscillator status 0. */
volatile uint32_t osc1_cfg0; /**< RTC Oscillator Configuration 0. */
volatile uint32_t usb_pll_cfg0; /**< USB Phase lock look configuration. */
volatile uint32_t
ccu_periph_clk_gate_ctl; /**< Peripheral Clock Gate Control. */
volatile uint32_t
ccu_periph_clk_div_ctl0; /**< Peripheral Clock Divider Control. 0 */
volatile uint32_t
ccu_gpio_db_clk_ctl; /**< Peripheral Clock Divider Control 1. */
volatile uint32_t
ccu_ext_clock_ctl; /**< External Clock Control Register. */
/** Sensor Subsystem peripheral clock gate control. */
volatile uint32_t ccu_ss_periph_clk_gate_ctl;
volatile uint32_t ccu_lp_clk_ctl; /**< System Low Power Clock Control. */
volatile uint32_t reserved;
volatile uint32_t ccu_mlayer_ahb_ctl; /**< AHB Control Register. */
volatile uint32_t ccu_sys_clk_ctl; /**< System Clock Control Register. */
volatile uint32_t osc_lock_0; /**< Clocks Lock Register. */
} qm_scss_ccu_reg_t;
#define QM_SCSS_CCU ((qm_scss_ccu_reg_t *)SCSS_REGISTER_BASE)
/** Power Management register map. */
typedef struct {
volatile uint32_t p_lvl2; /**< Processor level 2 */
volatile uint32_t reserved[4];
volatile uint32_t pm1c; /**< Power management 1 control */
volatile uint32_t reserved1[9];
volatile uint32_t aon_vr; /**< AON Voltage Regulator */
volatile uint32_t plat3p3_vr; /**< Platform 3p3 voltage regulator */
volatile uint32_t plat1p8_vr; /**< Platform 1p8 voltage regulator */
volatile uint32_t host_vr; /**< Host Voltage Regulator */
volatile uint32_t slp_cfg; /**< Sleeping Configuration */
/** Power Management Network (PMNet) Control and Status */
volatile uint32_t pmnetcs;
volatile uint32_t pm_wait; /**< Power Management Wait */
volatile uint32_t reserved2;
volatile uint32_t p_sts; /**< Processor Status */
volatile uint32_t reserved3[3];
volatile uint32_t rstc; /**< Reset Control */
volatile uint32_t rsts; /**< Reset Status */
volatile uint32_t reserved4[6];
volatile uint32_t vr_lock; /**< Voltage regulator lock */
volatile uint32_t pm_lock; /**< Power Management Lock */
} qm_scss_pmu_reg_t;
#define QM_SCSS_PMU_BASE (0xB0800504)
#define QM_SCSS_PMU ((qm_scss_pmu_reg_t *)QM_SCSS_PMU_BASE)
#define QM_SS_CFG_ARC_RUN_REQ_A BIT(24)
#define QM_P_STS_HALT_INTERRUPT_REDIRECTION BIT(26)
#define QM_P_STS_ARC_HALT BIT(14)
#define QM_AON_VR_VSEL_MASK (0xFFE0)
#define QM_AON_VR_VSEL_1V2 (0x8)
#define QM_AON_VR_VSEL_1V35 (0xB)
#define QM_AON_VR_VSEL_1V8 (0x10)
#define QM_AON_VR_EN BIT(7)
#define QM_AON_VR_VSTRB BIT(5)
#define QM_SCSS_SLP_CFG_LPMODE_EN BIT(8)
#define QM_SCSS_SLP_CFG_RTC_DIS BIT(7)
#define QM_SCSS_PM1C_SLPEN BIT(13)
#define QM_SCSS_HOST_VR_EN BIT(7)
#define QM_SCSS_PLAT3P3_VR_EN BIT(7)
#define QM_SCSS_PLAT1P8_VR_EN BIT(7)
#define QM_SCSS_HOST_VR_VREG_SEL BIT(6)
#define QM_SCSS_PLAT3P3_VR_VREG_SEL BIT(6)
#define QM_SCSS_PLAT1P8_VR_VREG_SEL BIT(6)
#define QM_SCSS_VR_ROK BIT(10)
#define QM_SCSS_VR_EN BIT(7)
#define QM_SCSS_VR_VREG_SEL BIT(6)
#define QM_SCSS_CCU_SS_LPS_EN BIT(0)
typedef enum {
QM_SS_IRQ_LEVEL_SENSITIVE = 0,
QM_SS_IRQ_EDGE_SENSITIVE = 1
} qm_ss_irq_trigger_t;
#define QM_SS_AUX_IRQ_CTRL (0xE)
#define QM_SS_AUX_IRQ_HINT (0x201)
#define QM_SS_AUX_IRQ_PRIORITY (0x206)
#define QM_SS_AUX_IRQ_STATUS (0x406)
#define QM_SS_AUX_IRQ_SELECT (0x40B)
#define QM_SS_AUX_IRQ_ENABLE (0x40C)
#define QM_SS_AUX_IRQ_TRIGGER (0x40D)
/** Always-On Timer Interrupt. */
#define QM_IRQ_AONPT_0_INT 28
#define QM_IRQ_AONPT_0_INT_MASK_OFFSET 32
#define QM_IRQ_AONPT_0_INT_VECTOR 64
/** RTC Single Interrupt. */
#define QM_IRQ_RTC_0_INT 11
#define QM_IRQ_RTC_0_INT_MASK_OFFSET 12
#define QM_IRQ_RTC_0_INT_VECTOR 47
/** @} */
/**
* @name SS Timer
* @{
*/
typedef enum {
QM_SS_TIMER_COUNT = 0,
QM_SS_TIMER_CONTROL,
QM_SS_TIMER_LIMIT
} qm_ss_timer_reg_t;
/**
* Sensor Subsystem Timers.
*/
typedef enum { QM_SS_TIMER_0 = 0, QM_SS_TIMER_NUM } qm_ss_timer_t;
/*
* SS TIMER context type.
*
* Application should not modify the content.
* This structure is only intended to be used by the qm_ss_timer_save_context
* and qm_ss_timer_restore_context functions.
*/
typedef struct {
uint32_t timer_count; /**< Timer count. */
uint32_t timer_control; /**< Timer control. */
uint32_t timer_limit; /**< Timer limit. */
} qm_ss_timer_context_t;
#define QM_SS_TIMER_0_BASE (0x21)
#define QM_SS_TIMER_1_BASE (0x100)
#define QM_SS_TSC_BASE QM_SS_TIMER_1_BASE
#define QM_SS_TIMER_CONTROL_INT_EN_OFFSET (0)
#define QM_SS_TIMER_CONTROL_NON_HALTED_OFFSET (1)
#define QM_SS_TIMER_CONTROL_WATCHDOG_OFFSET (2)
#define QM_SS_TIMER_CONTROL_INT_PENDING_OFFSET (3)
/** @} */
/**
* GPIO registers and definitions.
*
* @name SS GPIO
* @{
*/
/** Sensor Subsystem GPIO register block type. */
typedef enum {
QM_SS_GPIO_SWPORTA_DR = 0,
QM_SS_GPIO_SWPORTA_DDR,
QM_SS_GPIO_INTEN = 3,
QM_SS_GPIO_INTMASK,
QM_SS_GPIO_INTTYPE_LEVEL,
QM_SS_GPIO_INT_POLARITY,
QM_SS_GPIO_INTSTATUS,
QM_SS_GPIO_DEBOUNCE,
QM_SS_GPIO_PORTA_EOI,
QM_SS_GPIO_EXT_PORTA,
QM_SS_GPIO_LS_SYNC
} qm_ss_gpio_reg_t;
/**
* SS GPIO context type.
*
* Application should not modify the content.
* This structure is only intended to be used by the qm_ss_gpio_save_context and
* qm_ss_gpio_restore_context functions.
*/
typedef struct {
uint32_t gpio_swporta_dr; /**< Port A Data. */
uint32_t gpio_swporta_ddr; /**< Port A Data Direction. */
uint32_t gpio_inten; /**< Interrupt Enable. */
uint32_t gpio_intmask; /**< Interrupt Mask. */
uint32_t gpio_inttype_level; /**< Interrupt Type. */
uint32_t gpio_int_polarity; /**< Interrupt Polarity. */
uint32_t gpio_debounce; /**< Debounce Enable. */
uint32_t gpio_ls_sync; /**< Synchronization Level. */
} qm_ss_gpio_context_t;
#define QM_SS_GPIO_NUM_PINS (16)
#define QM_SS_GPIO_LS_SYNC_CLK_EN BIT(31)
#define QM_SS_GPIO_LS_SYNC_SYNC_LVL BIT(0)
/** Sensor Subsystem GPIO. */
typedef enum { QM_SS_GPIO_0 = 0, QM_SS_GPIO_1, QM_SS_GPIO_NUM } qm_ss_gpio_t;
#define QM_SS_GPIO_0_BASE (0x80017800)
#define QM_SS_GPIO_1_BASE (0x80017900)
/** @} */
/**
* I2C registers and definitions.
*
* @name SS I2C
* @{
*/
/** Sensor Subsystem I2C register block type. */
typedef enum {
QM_SS_I2C_CON = 0,
QM_SS_I2C_DATA_CMD,
QM_SS_I2C_SS_SCL_CNT,
QM_SS_I2C_FS_SCL_CNT = 0x04,
QM_SS_I2C_INTR_STAT = 0x06,
QM_SS_I2C_INTR_MASK,
QM_SS_I2C_TL,
QM_SS_I2C_INTR_CLR = 0x0A,
QM_SS_I2C_STATUS,
QM_SS_I2C_TXFLR,
QM_SS_I2C_RXFLR,
QM_SS_I2C_SDA_CONFIG,
QM_SS_I2C_TX_ABRT_SOURCE,
QM_SS_I2C_ENABLE_STATUS = 0x11
} qm_ss_i2c_reg_t;
/**
* SS I2C context type.
*
* Application should not modify the content.
* This structure is only intended to be used by the qm_ss_gpio_save_context and
* qm_ss_gpio_restore_context functions.
*/
typedef struct {
uint32_t i2c_con;
uint32_t i2c_ss_scl_cnt;
uint32_t i2c_fs_scl_cnt;
} qm_ss_i2c_context_t;
#define QM_SS_I2C_CON_ENABLE BIT(0)
#define QM_SS_I2C_CON_ABORT BIT(1)
#define QM_SS_I2C_CON_SPEED_SS BIT(3)
#define QM_SS_I2C_CON_SPEED_FS BIT(4)
#define QM_SS_I2C_CON_SPEED_MASK (0x18)
#define QM_SS_I2C_CON_IC_10BITADDR BIT(5)
#define QM_SS_I2C_CON_IC_10BITADDR_OFFSET (5)
#define QM_SS_I2C_CON_IC_10BITADDR_MASK (5)
#define QM_SS_I2C_CON_RESTART_EN BIT(7)
#define QM_SS_I2C_CON_TAR_SAR_OFFSET (9)
#define QM_SS_I2C_CON_TAR_SAR_MASK (0x7FE00)
#define QM_SS_I2C_CON_TAR_SAR_10_BIT_MASK (0x3FF)
#define QM_SS_I2C_CON_SPKLEN_OFFSET (22)
#define QM_SS_I2C_CON_SPKLEN_MASK (0x3FC00000)
#define QM_SS_I2C_CON_CLK_ENA BIT(31)
#define QM_SS_I2C_DATA_CMD_CMD BIT(8)
#define QM_SS_I2C_DATA_CMD_STOP BIT(9)
#define QM_SS_I2C_DATA_CMD_PUSH (0xC0000000)
#define QM_SS_I2C_DATA_CMD_POP (0x80000000)
#define QM_SS_I2C_SS_FS_SCL_CNT_HCNT_OFFSET (16)
#define QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK (0xFFFF)
#define QM_SS_I2C_INTR_STAT_RX_UNDER BIT(0)
#define QM_SS_I2C_INTR_STAT_RX_OVER BIT(1)
#define QM_SS_I2C_INTR_STAT_RX_FULL BIT(2)
#define QM_SS_I2C_INTR_STAT_TX_OVER BIT(3)
#define QM_SS_I2C_INTR_STAT_TX_EMPTY BIT(4)
#define QM_SS_I2C_INTR_STAT_TX_ABRT BIT(6)
#define QM_SS_I2C_INTR_MASK_ALL (0x0)
#define QM_SS_I2C_INTR_MASK_RX_UNDER BIT(0)
#define QM_SS_I2C_INTR_MASK_RX_OVER BIT(1)
#define QM_SS_I2C_INTR_MASK_RX_FULL BIT(2)
#define QM_SS_I2C_INTR_MASK_TX_OVER BIT(3)
#define QM_SS_I2C_INTR_MASK_TX_EMPTY BIT(4)
#define QM_SS_I2C_INTR_MASK_TX_ABRT BIT(6)
#define QM_SS_I2C_TL_TX_TL_OFFSET (16)
#define QM_SS_I2C_TL_RX_TL_MASK (0xFF)
#define QM_SS_I2C_TL_TX_TL_MASK (0xFF0000)
#define QM_SS_I2C_INTR_CLR_ALL (0xFF)
#define QM_SS_I2C_INTR_CLR_TX_ABRT BIT(6)
#define QM_SS_I2C_TX_ABRT_SOURCE_NAK_MASK (0x09)
#define QM_SS_I2C_TX_ABRT_SOURCE_ALL_MASK (0x1FFFF)
#define QM_SS_I2C_TX_ABRT_SBYTE_NORSTRT BIT(9)
#define QM_SS_I2C_TX_ABRT_SOURCE_ART_LOST BIT(12)
#define QM_SS_I2C_ENABLE_CONTROLLER_EN BIT(0)
#define QM_SS_I2C_ENABLE_STATUS_IC_EN BIT(0)
#define QM_SS_I2C_STATUS_BUSY_MASK (0x21)
#define QM_SS_I2C_STATUS_RFNE BIT(3)
#define QM_SS_I2C_STATUS_TFE BIT(2)
#define QM_SS_I2C_STATUS_TFNF BIT(1)
#define QM_SS_I2C_IC_LCNT_MAX (65525)
#define QM_SS_I2C_IC_LCNT_MIN (8)
#define QM_SS_I2C_IC_HCNT_MAX (65525)
#define QM_SS_I2C_IC_HCNT_MIN (6)
#define QM_SS_I2C_FIFO_SIZE (8)
/** Sensor Subsystem I2C */
typedef enum { QM_SS_I2C_0 = 0, QM_SS_I2C_1, QM_SS_I2C_NUM } qm_ss_i2c_t;
#define QM_SS_I2C_0_BASE (0x80012000)
#define QM_SS_I2C_1_BASE (0x80012100)
/** @} */
/** Sensor Subsystem ADC @{*/
/** Sensor Subsystem ADC registers */
typedef enum {
QM_SS_ADC_SET = 0, /**< ADC and sequencer settings register. */
QM_SS_ADC_DIVSEQSTAT, /**< ADC clock and sequencer status register. */
QM_SS_ADC_SEQ, /**< ADC sequence entry register. */
QM_SS_ADC_CTRL, /**< ADC control register. */
QM_SS_ADC_INTSTAT, /**< ADC interrupt status register. */
QM_SS_ADC_SAMPLE /**< ADC sample register. */
} qm_ss_adc_reg_t;
/** Sensor Subsystem ADC */
typedef enum {
QM_SS_ADC_0 = 0, /**< ADC first module. */
QM_SS_ADC_NUM
} qm_ss_adc_t;
/**
* SS ADC context type.
*
* The application should not modify the content of this structure.
*
* This structure is intented to be used by qm_ss_adc_save_context and
* qm_ss_adc_restore_context functions only.
*/
typedef struct {
uint32_t adc_set; /**< ADC settings. */
uint32_t adc_divseqstat; /**< ADC clock divider and sequencer status. */
uint32_t adc_seq; /**< ADC sequencer entry. */
uint32_t adc_ctrl; /**< ADC control. */
} qm_ss_adc_context_t;
/* SS ADC register base. */
#define QM_SS_ADC_BASE (0x80015000)
/* For 1MHz, the max divisor is 7. */
#define QM_SS_ADC_DIV_MAX (7)
#define QM_SS_ADC_FIFO_LEN (32)
#define QM_SS_ADC_SET_POP_RX BIT(31)
#define QM_SS_ADC_SET_FLUSH_RX BIT(30)
#define QM_SS_ADC_SET_THRESHOLD_MASK (0x3F000000)
#define QM_SS_ADC_SET_THRESHOLD_OFFSET (24)
#define QM_SS_ADC_SET_SEQ_ENTRIES_MASK (0x3F0000)
#define QM_SS_ADC_SET_SEQ_ENTRIES_OFFSET (16)
#define QM_SS_ADC_SET_SEQ_MODE BIT(13)
#define QM_SS_ADC_SET_SAMPLE_WIDTH_MASK (0x1F)
#define QM_SS_ADC_DIVSEQSTAT_CLK_RATIO_MASK (0x1FFFFF)
#define QM_SS_ADC_CTRL_CLR_SEQERROR BIT(19)
#define QM_SS_ADC_CTRL_CLR_UNDERFLOW BIT(18)
#define QM_SS_ADC_CTRL_CLR_OVERFLOW BIT(17)
#define QM_SS_ADC_CTRL_CLR_DATA_A BIT(16)
#define QM_SS_ADC_CTRL_MSK_SEQERROR BIT(11)
#define QM_SS_ADC_CTRL_MSK_UNDERFLOW BIT(10)
#define QM_SS_ADC_CTRL_MSK_OVERFLOW BIT(9)
#define QM_SS_ADC_CTRL_MSK_DATA_A BIT(8)
#define QM_SS_ADC_CTRL_SEQ_TABLE_RST BIT(6)
#define QM_SS_ADC_CTRL_SEQ_PTR_RST BIT(5)
#define QM_SS_ADC_CTRL_SEQ_START BIT(4)
#define QM_SS_ADC_CTRL_CLK_ENA BIT(2)
#define QM_SS_ADC_CTRL_ADC_ENA BIT(1)
#define QM_SS_ADC_CTRL_MSK_ALL_INT (0xF00)
#define QM_SS_ADC_CTRL_CLR_ALL_INT (0xF0000)
#define QM_SS_ADC_SEQ_DELAYODD_OFFSET (21)
#define QM_SS_ADC_SEQ_MUXODD_OFFSET (16)
#define QM_SS_ADC_SEQ_DELAYEVEN_OFFSET (5)
#define QM_SS_ADC_SEQ_DUMMY (0x480)
#define QM_SS_ADC_INTSTAT_SEQERROR BIT(3)
#define QM_SS_ADC_INTSTAT_UNDERFLOW BIT(2)
#define QM_SS_ADC_INTSTAT_OVERFLOW BIT(1)
#define QM_SS_ADC_INTSTAT_DATA_A BIT(0)
/** End of Sensor Subsystem ADC @}*/
/**
* CREG Registers.
*
* @name SS CREG
* @{
*/
/* Sensor Subsystem CREG */
typedef enum {
QM_SS_IO_CREG_MST0_CTRL = 0x0, /**< Master control register. */
QM_SS_IO_CREG_SLV0_OBSR = 0x80, /**< Slave control register. */
QM_SS_IO_CREG_SLV1_OBSR = 0x180 /**< Slave control register. */
} qm_ss_creg_reg_t;
/* MST0_CTRL fields */
#define QM_SS_IO_CREG_MST0_CTRL_ADC_PWR_MODE_OFFSET (1)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_PWR_MODE_MASK (0x7)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_DELAY_OFFSET (3)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_DELAY_MASK (0xFFF8)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_REQ BIT(16)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_CMD_OFFSET (17)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_CMD_MASK (0xE0000)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_VAL_OFFSET (20)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_VAL_MASK (0x7F00000)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_VAL_MAX (0x7F)
#define QM_SS_IO_CREG_MST0_CTRL_SPI1_CLK_GATE BIT(27)
#define QM_SS_IO_CREG_MST0_CTRL_SPI0_CLK_GATE BIT(28)
#define QM_SS_IO_CREG_MST0_CTRL_I2C0_CLK_GATE BIT(29)
#define QM_SS_IO_CREG_MST0_CTRL_I2C1_CLK_GATE BIT(30)
#define QM_SS_IO_CREG_MST0_CTRL_ADC_CLK_GATE BIT(31)
/* SLV0_OBSR fields */
#define QM_SS_IO_CREG_SLV0_OBSR_ADC_CAL_VAL_OFFSET (5)
#define QM_SS_IO_CREG_SLV0_OBSR_ADC_CAL_VAL_MASK (0xFE0)
#define QM_SS_IO_CREG_SLV0_OBSR_ADC_CAL_ACK BIT(4)
#define QM_SS_IO_CREG_SLV0_OBSR_ADC_PWR_MODE_STS BIT(3)
#define SS_CLK_PERIPH_ALL_IN_CREG \
(SS_CLK_PERIPH_ADC | SS_CLK_PERIPH_I2C_1 | SS_CLK_PERIPH_I2C_0 | \
SS_CLK_PERIPH_SPI_1 | SS_CLK_PERIPH_SPI_0)
/* SS CREG base. */
#define QM_SS_CREG_BASE (0x80018000)
/** @} */
/**
* I2C registers and definitions.
*
* @name SS SPI
* @{
*/
/** Sensor Subsystem SPI register map. */
typedef enum {
QM_SS_SPI_CTRL = 0, /**< SPI control register. */
QM_SS_SPI_SPIEN = 2, /**< SPI enable register. */
QM_SS_SPI_TIMING = 4, /**< SPI serial clock divider value. */
QM_SS_SPI_FTLR, /**< Threshold value for TX/RX FIFO. */
QM_SS_SPI_TXFLR = 7, /**< Number of valid data entries in TX FIFO. */
QM_SS_SPI_RXFLR, /**< Number of valid data entries in RX FIFO. */
QM_SS_SPI_SR, /**< SPI status register. */
QM_SS_SPI_INTR_STAT, /**< Interrupt status register. */
QM_SS_SPI_INTR_MASK, /**< Interrupt mask register. */
QM_SS_SPI_CLR_INTR, /**< Interrupt clear register. */
QM_SS_SPI_DR, /**< RW buffer for FIFOs. */
} qm_ss_spi_reg_t;
/**
* Sensor Subsystem SPI context type.
*
* Applications should not modify the content.
* This structure is only intended to be used by
* the qm_ss_spi_save_context and qm_ss_spi_restore_context functions.
*/
typedef struct {
uint32_t spi_ctrl; /**< Control Register. */
uint32_t spi_spien; /**< SPI Enable Register. */
uint32_t spi_timing; /**< Timing Register. */
} qm_ss_spi_context_t;
/** Sensor Subsystem SPI modules. */
typedef enum {
QM_SS_SPI_0 = 0, /**< SPI module 0 */
QM_SS_SPI_1, /**< SPI module 1 */
QM_SS_SPI_NUM
} qm_ss_spi_t;
#define QM_SS_SPI_0_BASE (0x80010000)
#define QM_SS_SPI_1_BASE (0x80010100)
#define QM_SS_SPI_CTRL_DFS_OFFS (0)
#define QM_SS_SPI_CTRL_DFS_MASK (0x0000000F)
#define QM_SS_SPI_CTRL_BMOD_OFFS (6)
#define QM_SS_SPI_CTRL_BMOD_MASK (0x000000C0)
#define QM_SS_SPI_CTRL_SCPH BIT(6)
#define QM_SS_SPI_CTRL_SCPOL BIT(7)
#define QM_SS_SPI_CTRL_TMOD_OFFS (8)
#define QM_SS_SPI_CTRL_TMOD_MASK (0x00000300)
#define QM_SS_SPI_CTRL_SRL BIT(11)
#define QM_SS_SPI_CTRL_CLK_ENA BIT(15)
#define QM_SS_SPI_CTRL_NDF_OFFS (16)
#define QM_SS_SPI_CTRL_NDF_MASK (0xFFFF0000)
#define QM_SS_SPI_SPIEN_EN BIT(0)
#define QM_SS_SPI_SPIEN_SER_OFFS (4)
#define QM_SS_SPI_SPIEN_SER_MASK (0x000000F0)
#define QM_SS_SPI_TIMING_SCKDV_OFFS (0)
#define QM_SS_SPI_TIMING_SCKDV_MASK (0x0000FFFF)
#define QM_SS_SPI_TIMING_RSD_OFFS (16)
#define QM_SS_SPI_TIMING_RSD_MASK (0x00FF0000)
#define QM_SS_SPI_FTLR_RFT_OFFS (0)
#define QM_SS_SPI_FTLR_RFT_MASK (0x0000FFFF)
#define QM_SS_SPI_FTLR_TFT_OFFS (16)
#define QM_SS_SPI_FTLR_TFT_MASK (0xFFFF0000)
#define QM_SS_SPI_SR_BUSY BIT(0)
#define QM_SS_SPI_SR_TFNF BIT(1)
#define QM_SS_SPI_SR_TFE BIT(2)
#define QM_SS_SPI_SR_RFNE BIT(3)
#define QM_SS_SPI_SR_RFF BIT(4)
#define QM_SS_SPI_INTR_TXEI BIT(0)
#define QM_SS_SPI_INTR_TXOI BIT(1)
#define QM_SS_SPI_INTR_RXUI BIT(2)
#define QM_SS_SPI_INTR_RXOI BIT(3)
#define QM_SS_SPI_INTR_RXFI BIT(4)
#define QM_SS_SPI_INTR_ALL (0x0000001F)
#define QM_SS_SPI_INTR_STAT_TXEI QM_SS_SPI_INTR_TXEI
#define QM_SS_SPI_INTR_STAT_TXOI QM_SS_SPI_INTR_TXOI
#define QM_SS_SPI_INTR_STAT_RXUI QM_SS_SPI_INTR_RXUI
#define QM_SS_SPI_INTR_STAT_RXOI QM_SS_SPI_INTR_RXOI
#define QM_SS_SPI_INTR_STAT_RXFI QM_SS_SPI_INTR_RXFI
#define QM_SS_SPI_INTR_MASK_TXEI QM_SS_SPI_INTR_TXEI
#define QM_SS_SPI_INTR_MASK_TXOI QM_SS_SPI_INTR_TXOI
#define QM_SS_SPI_INTR_MASK_RXUI QM_SS_SPI_INTR_RXUI
#define QM_SS_SPI_INTR_MASK_RXOI QM_SS_SPI_INTR_RXOI
#define QM_SS_SPI_INTR_MASK_RXFI QM_SS_SPI_INTR_RXFI
#define QM_SS_SPI_CLR_INTR_TXEI QM_SS_SPI_INTR_TXEI
#define QM_SS_SPI_CLR_INTR_TXOI QM_SS_SPI_INTR_TXOI
#define QM_SS_SPI_CLR_INTR_RXUI QM_SS_SPI_INTR_RXUI
#define QM_SS_SPI_CLR_INTR_RXOI QM_SS_SPI_INTR_RXOI
#define QM_SS_SPI_CLR_INTR_RXFI QM_SS_SPI_INTR_RXFI
#define QM_SS_SPI_DR_DR_OFFS (0)
#define QM_SS_SPI_DR_DR_MASK (0x0000FFFF)
#define QM_SS_SPI_DR_WR BIT(30)
#define QM_SS_SPI_DR_STROBE BIT(31)
#define QM_SS_SPI_DR_W_MASK (0xc0000000)
#define QM_SS_SPI_DR_R_MASK (0x80000000)
/** @} */
/** @} */
#endif /* __SENSOR_REGISTERS_H__ */

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/*
* Copyright (c) 2016, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __QM_SOC_INTERRUPTS_H__
#define __QM_SOC_INTERRUPTS_H__
/**
* Quark SE SoC Interrupts.
*
* @defgroup groupQUARKSESEINT SoC Interrupts (SE)
* @{
*/
#if (QM_LAKEMONT)
/* x86 internal interrupt vectors. */
#define QM_X86_DIVIDE_ERROR_INT (0)
#define QM_X86_DEBUG_EXCEPTION_INT (1)
#define QM_X86_NMI_INTERRUPT_INT (2)
#define QM_X86_BREAKPOINT_INT (3)
#define QM_X86_OVERFLOW_INT (4)
#define QM_X86_BOUND_RANGE_EXCEEDED_INT (5)
#define QM_X86_INVALID_OPCODE_INT (6)
#define QM_X86_DEVICE_NOT_AVAILABLE_INT (7)
#define QM_X86_DOUBLE_FAULT_INT (8)
#define QM_X86_INTEL_RESERVED_09_INT (9)
#define QM_X86_INVALID_TSS_INT (10)
#define QM_X86_SEGMENT_NOT_PRESENT_INT (11)
#define QM_X86_STACK_SEGMENT_FAULT_INT (12)
#define QM_X86_GENERAL_PROTECT_FAULT_INT (13)
#define QM_X86_PAGE_FAULT_INT (14)
#define QM_X86_INTEL_RESERVED_15_INT (15)
#define QM_X86_FLOATING_POINT_ERROR_INT (16)
#define QM_X86_ALIGNMENT_CHECK_INT (17)
#define QM_X86_INTEL_RESERVED_18_INT (18)
#define QM_X86_INTEL_RESERVED_19_INT (19)
#define QM_X86_INTEL_RESERVED_20_INT (20)
#define QM_X86_INTEL_RESERVED_21_INT (21)
#define QM_X86_INTEL_RESERVED_22_INT (22)
#define QM_X86_INTEL_RESERVED_23_INT (23)
#define QM_X86_INTEL_RESERVED_24_INT (24)
#define QM_X86_INTEL_RESERVED_25_INT (25)
#define QM_X86_INTEL_RESERVED_26_INT (26)
#define QM_X86_INTEL_RESERVED_27_INT (27)
#define QM_X86_INTEL_RESERVED_28_INT (28)
#define QM_X86_INTEL_RESERVED_29_INT (29)
#define QM_X86_INTEL_RESERVED_30_INT (30)
#define QM_X86_INTEL_RESERVED_31_INT (31)
#define QM_X86_PIC_TIMER_INT_VECTOR (32)
#endif /* QM_LAKEMONT */
#if (QM_SENSOR)
/* ARC EM processor internal interrupt vector assignments. */
#define QM_ARC_RESET_INT (0)
#define QM_ARC_MEMORY_ERROR_INT (1)
#define QM_ARC_INSTRUCTION_ERROR_INT (2)
#define QM_ARC_MACHINE_CHECK_EXCEPTION_INT (3)
#define QM_ARC_INSTRUCTION_TLB_MISS_INT (4)
#define QM_ARC_DATA_TLB_MISS_INT (5)
#define QM_ARC_PROTECTION_VIOLATION_INT (6)
#define QM_ARC_PRIVILEGE_VIOLATION_INT (7)
#define QM_ARC_SOFTWARE_INTERRUPT_INT (8)
#define QM_ARC_TRAP_INT (9)
#define QM_ARC_EXTENSION_INSTRUCTION_EXCEPTION_INT (10)
#define QM_ARC_DIVIDE_BY_ZERO_INT (11)
#define QM_ARC_DATA_CACHE_CONSISTENCY_ERROR_INT (12)
#define QM_ARC_MISALIGNED_DATA_ACCESS_INT (13)
#define QM_ARC_RESERVED_14_INT (14)
#define QM_ARC_RESERVED_15_INT (15)
#define QM_ARC_TIMER_0_INT (16)
#define QM_ARC_TIMER_1_INT (17)
#endif /* QM_SENSOR */
#if (QM_SENSOR)
/**
* Sensor Sub-System Specific IRQs and interrupt vectors.
*
* @name SS Interrupt
* @{
*/
#define QM_SS_EXCEPTION_NUM (16) /* Exceptions and traps in ARC EM core. */
#define QM_SS_INT_TIMER_NUM (2) /* Internal interrupts in ARC EM core. */
#define QM_SS_IRQ_SENSOR_NUM (18) /* IRQ's from the Sensor Subsystem. */
#define QM_SS_IRQ_COMMON_NUM (32) /* IRQ's from the common SoC fabric. */
#define QM_SS_INT_VECTOR_NUM \
(QM_SS_EXCEPTION_NUM + QM_SS_INT_TIMER_NUM + QM_SS_IRQ_SENSOR_NUM + \
QM_SS_IRQ_COMMON_NUM)
#define QM_SS_IRQ_NUM (QM_SS_IRQ_SENSOR_NUM + QM_SS_IRQ_COMMON_NUM)
/*
* The following definitions are Sensor Subsystem interrupt irq and vector
* numbers:
* #define QM_SS_xxx - irq number
* #define QM_SS_xxx_VECTOR - vector number
*/
/** Sensor Subsystem ADC Rx Fifo Error Interrupt. */
#define QM_SS_IRQ_ADC_0_ERROR_INT 0
#define QM_SS_IRQ_ADC_0_ERROR_INT_VECTOR 18
/** Sensor Subsystem ADC Data Available Interrupt. */
#define QM_SS_IRQ_ADC_0_INT 1
#define QM_SS_IRQ_ADC_0_INT_VECTOR 19
/** Sensor Subsystem GPIO Single Interrupt 0 */
#define QM_SS_IRQ_GPIO_0_INT 2
#define QM_SS_IRQ_GPIO_0_INT_VECTOR 20
/** Sensor Subsystem GPIO Single Interrupt 1. */
#define QM_SS_IRQ_GPIO_1_INT 3
#define QM_SS_IRQ_GPIO_1_INT_VECTOR 21
/** Sensor Subsystem I2C 0 Error Interrupt. */
#define QM_SS_IRQ_I2C_0_ERROR_INT 4
#define QM_SS_IRQ_I2C_0_ERROR_INT_VECTOR 22
/** Sensor Subsystem I2C 0 Data Available Interrupt. */
#define QM_SS_IRQ_I2C_0_RX_AVAIL_INT 5
#define QM_SS_IRQ_I2C_0_RX_AVAIL_INT_VECTOR 23
/** Sensor Subsystem I2C 0 Data Required Interrupt. */
#define QM_SS_IRQ_I2C_0_TX_REQ_INT 6
#define QM_SS_IRQ_I2C_0_TX_REQ_INT_VECTOR 24
/** Sensor Subsystem I2C 0 Stop Detect Interrupt. */
#define QM_SS_IRQ_I2C_0_STOP_DET_INT 7
#define QM_SS_IRQ_I2C_0_STOP_DET_INT_VECTOR 25
/** Sensor Subsystem I2C 1 Error Interrupt. */
#define QM_SS_IRQ_I2C_1_ERROR_INT 8
#define QM_SS_IRQ_I2C_1_ERROR_INT_VECTOR 26
/** Sensor Subsystem I2C 1 Data Available Interrupt. */
#define QM_SS_IRQ_I2C_1_RX_AVAIL_INT 9
#define QM_SS_IRQ_I2C_1_RX_AVAIL_INT_VECTOR 27
/** Sensor Subsystem I2C 1 Data Required Interrupt. */
#define QM_SS_IRQ_I2C_1_TX_REQ_INT 10
#define QM_SS_IRQ_I2C_1_TX_REQ_INT_VECTOR 28
/** Sensor Subsystem I2C 1 Stop Detect Interrupt. */
#define QM_SS_IRQ_I2C_1_STOP_DET_INT 11
#define QM_SS_IRQ_I2C_1_STOP_DET_INT_VECTOR 29
/** Sensor Subsystem SPI 0 Error Interrupt. */
#define QM_SS_IRQ_SPI_0_ERROR_INT 12
#define QM_SS_IRQ_SPI_0_ERROR_INT_VECTOR 30
/** Sensor Subsystem SPI 0 Data Available Interrupt. */
#define QM_SS_IRQ_SPI_0_RX_AVAIL_INT 13
#define QM_SS_IRQ_SPI_0_RX_AVAIL_INT_VECTOR 31
/** Sensor Subsystem SPI 0 Data Required Interrupt. */
#define QM_SS_IRQ_SPI_0_TX_REQ_INT 14
#define QM_SS_IRQ_SPI_0_TX_REQ_INT_VECTOR 32
/** Sensor Subsystem SPI 1 Error Interrupt. */
#define QM_SS_IRQ_SPI_1_ERROR_INT 15
#define QM_SS_IRQ_SPI_1_ERROR_INT_VECTOR 33
/** Sensor Subsystem SPI 1 Data Available Interrupt. */
#define QM_SS_IRQ_SPI_1_RX_AVAIL_INT 16
#define QM_SS_IRQ_SPI_1_RX_AVAIL_INT_VECTOR 34
/** Sensor Subsystem SPI 1 Data Required Interrupt. */
#define QM_SS_IRQ_SPI_1_TX_REQ_INT 17
#define QM_SS_IRQ_SPI_1_TX_REQ_INT_VECTOR 35
typedef enum {
QM_SS_INT_PRIORITY_0 = 0,
QM_SS_INT_PRIORITY_1 = 1,
QM_SS_INT_PRIORITY_15 = 15,
QM_SS_INT_PRIORITY_NUM
} qm_ss_irq_priority_t;
typedef enum { QM_SS_INT_DISABLE = 0, QM_SS_INT_ENABLE = 1 } qm_ss_irq_mask_t;
typedef enum {
QM_SS_IRQ_LEVEL_SENSITIVE = 0,
QM_SS_IRQ_EDGE_SENSITIVE = 1
} qm_ss_irq_trigger_t;
#define QM_SS_AUX_IRQ_CTRL (0xE)
#define QM_SS_AUX_IRQ_HINT (0x201)
#define QM_SS_AUX_IRQ_PRIORITY (0x206)
#define QM_SS_AUX_IRQ_STATUS (0x406)
#define QM_SS_AUX_IRQ_SELECT (0x40B)
#define QM_SS_AUX_IRQ_ENABLE (0x40C)
#define QM_SS_AUX_IRQ_TRIGGER (0x40D)
/** @} */
#endif /* QM_SENSOR */
/**
* @name Common SoC IRQs and Interrupts
* @{
*/
/* IRQs and interrupt vectors.
*
* Any IRQ > 1 actually has a event router mask register offset of +1.
* The vector numbers must be defined without arithmetic expressions nor
* parentheses because they are expanded as token concatenation.
*/
/** I2C Master 0 Single Interrupt. */
#define QM_IRQ_I2C_0_INT 0
#define QM_IRQ_I2C_0_INT_MASK_OFFSET 0
#define QM_IRQ_I2C_0_INT_VECTOR 36
/** I2C Master 1 Single Interrupt. */
#define QM_IRQ_I2C_1_INT 1
#define QM_IRQ_I2C_1_INT_MASK_OFFSET 1
#define QM_IRQ_I2C_1_INT_VECTOR 37
/** SPI Master 0 Single Interrupt. */
#define QM_IRQ_SPI_MASTER_0_INT 2
#define QM_IRQ_SPI_MASTER_0_INT_MASK_OFFSET 3
#define QM_IRQ_SPI_MASTER_0_INT_VECTOR 38
/** SPI Master 1 Single Interrupt. */
#define QM_IRQ_SPI_MASTER_1_INT 3
#define QM_IRQ_SPI_MASTER_1_INT_MASK_OFFSET 4
#define QM_IRQ_SPI_MASTER_1_INT_VECTOR 39
/** SPI Slave Single Interrupt. */
#define QM_IRQ_SPI_SLAVE_0_INT 4
#define QM_IRQ_SPI_SLAVE_0_INT_MASK_OFFSET 5
#define QM_IRQ_SPI_SLAVE_0_INT_VECTOR 40
/** UART 0 Single Interrupt. */
#define QM_IRQ_UART_0_INT 5
#define QM_IRQ_UART_0_INT_MASK_OFFSET 6
#define QM_IRQ_UART_0_INT_VECTOR 41
/** UART 1 Single Interrupt. */
#define QM_IRQ_UART_1_INT 6
#define QM_IRQ_UART_1_INT_MASK_OFFSET 7
#define QM_IRQ_UART_1_INT_VECTOR 42
/** I2S Single Interrupt. */
#define QM_IRQ_I2S_0_INT 7
#define QM_IRQ_I2S_0_INT_MASK_OFFSET 8
#define QM_IRQ_I2S_0_INT_VECTOR 43
/** GPIO Single Interrupt. */
#define QM_IRQ_GPIO_0_INT 8
#define QM_IRQ_GPIO_0_INT_MASK_OFFSET 9
#define QM_IRQ_GPIO_0_INT_VECTOR 44
/** PWM/Timer Single Interrupt. */
#define QM_IRQ_PWM_0_INT 9
#define QM_IRQ_PWM_0_INT_MASK_OFFSET 10
#define QM_IRQ_PWM_0_INT_VECTOR 45
/** USB Single Interrupt. */
#define QM_IRQ_USB_0_INT (10)
#define QM_IRQ_USB_0_INT_MASK_OFFSET (11)
#define QM_IRQ_USB_0_INT_VECTOR 46
/** RTC Single Interrupt. */
#define QM_IRQ_RTC_0_INT 11
#define QM_IRQ_RTC_0_INT_MASK_OFFSET 12
#define QM_IRQ_RTC_0_INT_VECTOR 47
/** WDT Single Interrupt. */
#define QM_IRQ_WDT_0_INT 12
#define QM_IRQ_WDT_0_INT_MASK_OFFSET 13
#define QM_IRQ_WDT_0_INT_VECTOR 48
/** DMA Channel 0 Single Interrupt. */
#define QM_IRQ_DMA_0_INT_0 13
#define QM_IRQ_DMA_0_INT_0_MASK_OFFSET 14
#define QM_IRQ_DMA_0_INT_0_VECTOR 49
/** DMA Channel 1 Single Interrupt. */
#define QM_IRQ_DMA_0_INT_1 14
#define QM_IRQ_DMA_0_INT_1_MASK_OFFSET 15
#define QM_IRQ_DMA_0_INT_1_VECTOR 50
/** DMA Channel 2 Single Interrupt. */
#define QM_IRQ_DMA_0_INT_2 15
#define QM_IRQ_DMA_0_INT_2_MASK_OFFSET 16
#define QM_IRQ_DMA_0_INT_2_VECTOR 51
/** DMA Channel 3 Single Interrupt. */
#define QM_IRQ_DMA_0_INT_3 16
#define QM_IRQ_DMA_0_INT_3_MASK_OFFSET 17
#define QM_IRQ_DMA_0_INT_3_VECTOR 52
/** DMA Channel 4 Single Interrupt. */
#define QM_IRQ_DMA_0_INT_4 17
#define QM_IRQ_DMA_0_INT_4_MASK_OFFSET 18
#define QM_IRQ_DMA_0_INT_4_VECTOR 53
/** DMA Channel 5 Single Interrupt. */
#define QM_IRQ_DMA_0_INT_5 18
#define QM_IRQ_DMA_0_INT_5_MASK_OFFSET 19
#define QM_IRQ_DMA_0_INT_5_VECTOR 54
/** DMA Channel 6 Single Interrupt. */
#define QM_IRQ_DMA_0_INT_6 19
#define QM_IRQ_DMA_0_INT_6_MASK_OFFSET 20
#define QM_IRQ_DMA_0_INT_6_VECTOR 55
/** DMA Channel 7 Single Interrupt. */
#define QM_IRQ_DMA_0_INT_7 20
#define QM_IRQ_DMA_0_INT_7_MASK_OFFSET 21
#define QM_IRQ_DMA_0_INT_7_VECTOR 56
/**
* 8 Mailbox Channel Interrupts Routed to Single Interrupt
* with 8bit Mask per Destination.
*/
#define QM_IRQ_MAILBOX_0_INT 21
#define QM_IRQ_MAILBOX_0_INT_MASK_OFFSET 22
#define QM_IRQ_MAILBOX_0_INT_VECTOR 57
/**
* 19 Comparators Routed to Single Interrupt with 19bit Mask per Destination.
*/
#define QM_IRQ_COMPARATOR_0_INT 22
#define QM_IRQ_COMPARATOR_0_INT_MASK_OFFSET 26
#define QM_IRQ_COMPARATOR_0_INT_VECTOR 58
/** System and Power Management Single Interrupt. */
#define QM_IRQ_PMU_0_INT 23
#define QM_IRQ_PMU_0_INT_MASK_OFFSET 26
#define QM_IRQ_PMU_0_INT_VECTOR 58
/**
* 8 DMA Channel Error Interrupts Routed to Single Interrupt with 8bit Mask
* per Destination.
*/
#define QM_IRQ_DMA_0_ERROR_INT 24
#define QM_IRQ_DMA_0_ERROR_INT_MASK_OFFSET 28
#define QM_IRQ_DMA_0_ERROR_INT_VECTOR 60
/** Internal SRAM Memory Protection Error Single Interrupt. */
#define QM_IRQ_SRAM_MPR_0_INT 25
#define QM_IRQ_SRAM_MPR_0_INT_MASK_OFFSET 29
#define QM_IRQ_SRAM_MPR_0_INT_VECTOR 61
/** Internal Flash Controller 0 Memory Protection Error Single Interrupt. */
#define QM_IRQ_FLASH_MPR_0_INT 26
#define QM_IRQ_FLASH_MPR_0_INT_MASK_OFFSET 30
#define QM_IRQ_FLASH_MPR_0_INT_VECTOR 62
/** Internal Flash Controller 1 Memory Protection Error Single Interrupt. */
#define QM_IRQ_FLASH_MPR_1_INT 27
#define QM_IRQ_FLASH_MPR_1_INT_MASK_OFFSET 31
#define QM_IRQ_FLASH_MPR_1_INT_VECTOR 63
/** Always-On Timer Interrupt. */
#define QM_IRQ_AONPT_0_INT 28
#define QM_IRQ_AONPT_0_INT_MASK_OFFSET 32
#define QM_IRQ_AONPT_0_INT_VECTOR 64
/** ADC power sequence done. */
#define QM_SS_IRQ_ADC_0_PWR_INT 29
#define QM_SS_IRQ_ADC_0_PWR_INT_MASK_OFFSET 33
#define QM_SS_IRQ_ADC_0_PWR_INT_VECTOR 65
/** ADC calibration done. */
#define QM_SS_IRQ_ADC_0_CAL_INT 30
#define QM_SS_IRQ_ADC_0_CAL_INT_MASK_OFFSET 34
#define QM_SS_IRQ_ADC_0_CAL_INT_VECTOR 66
/** Always-On GPIO Interrupt. */
#define QM_IRQ_AON_GPIO_0_INT 31
#define QM_IRQ_AON_GPIO_0_INT_MASK_OFFSET 35
#define QM_IRQ_AON_GPIO_0_INT_VECTOR 67
/** @} */
/** @} */
#endif /* __QM_SOC_INTERRUPTS_H__ */

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/*
* Copyright (c) 2016, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __QM_SS_POWER_STATES_H__
#define __QM_SS_POWER_STATES_H__
#include "qm_sensor_regs.h"
/**
* SS Power mode control for Quark SE Microcontrollers.
*
* @defgroup groupSSPower SS Power states
* @{
*/
/**
* Sensor Subsystem SS1 Timers mode type.
*/
typedef enum {
SS_POWER_CPU_SS1_TIMER_OFF = 0, /**< Disable SS Timers in SS1. */
SS_POWER_CPU_SS1_TIMER_ON /**< Keep SS Timers enabled in SS1. */
} ss_power_cpu_ss1_mode_t;
/**
* Enable LPSS state entry.
*
* Put the SoC into LPSS on next C2/C2LP and SS2 state combination.<BR>
* This function needs to be called on the Sensor Core to
* Clock Gate ADC, I2C0, I2C1, SPI0 and SPI1 sensor peripherals.<BR>
* Clock Gating sensor peripherals is a requirement to enter LPSS state.<BR>
* After LPSS, ss_power_soc_lpss_disable needs to be called to
* restore clock gating.<BR>
*
* This needs to be called before any transition to C2/C2LP and SS2
* in order to enter LPSS.<BR>
* SoC Hybrid Clock is gated in this state.<BR>
* Core Well Clocks are gated.<BR>
* RTC is the only clock running.
*
* Possible SoC wake events are:
* - Low Power Comparator Interrupt
* - AON GPIO Interrupt
* - AON Timer Interrupt
* - RTC Interrupt
*/
//void ss_power_soc_lpss_enable(void);
/**
* Enter SoC sleep state and restore after wake up.
*
* Put the ARC core into sleep state until next SoC wake event
* and continue execution after wake up where the application stopped.
*
* If the library is built with ENABLE_RESTORE_CONTEXT=1, then this function
* will use the arc_restore_addr to save restore trap address which brings back
* the ARC CPU to the point where this function was called.
* This means that applications should refrain from using them.
*
* This function calls qm_ss_save_context and qm_ss_restore_context
* in order to restore execution where it stopped.
* All power management transitions are done by power_soc_sleep().
*/
//void ss_power_soc_sleep_restore(void);
/**
* Enter SoC sleep state and restore after wake up.
*
* Put the ARC core into sleep state until next SoC wake event
* and continue execution after wake up where the application stopped.
*
* If the library is built with ENABLE_RESTORE_CONTEXT=1, then this function
* will use the arc_restore_addr to save restore trap address which brings back
* the ARC CPU to the point where this function was called.
* This means that applications should refrain from using them.
*
* This function calls qm_ss_save_context and qm_ss_restore_context
* in order to restore execution where it stopped.
* All power management transitions are done by power_soc_deep_sleep().
*/
//void ss_power_soc_deep_sleep_restore(void);
/**
* Save context, enter ARC SS1 power save state and restore after wake up.
*
* This routine is same as ss_power_soc_sleep_restore(), just instead of
* going to sleep it will go to SS1 power save state.
* Note: this function has a while(1) which will spin until we enter
* (and exit) sleep and the power state change will be managed by the other
* core.
*/
//void ss_power_sleep_wait(void);
/**
* Enable the SENSOR startup restore flag.
*/
//void power_soc_set_ss_restore_flag(void);
/**
* Disable LPSS state entry.
*
* Clear LPSS enable flag.<BR>
* Disable Clock Gating of ADC, I2C0, I2C1, SPI0 and SPI1 sensor
* peripherals.<BR>
* This will prevent entry in LPSS when cores are in C2/C2LP and SS2 states.
*/
//void ss_power_soc_lpss_disable(void);
/**
* Enter Sensor SS1 state.
*
* Put the Sensor Subsystem into SS1.<BR>
* Processor Clock is gated in this state.
*
* A wake event causes the Sensor Subsystem to transition to SS0.<BR>
* A wake event is a sensor subsystem interrupt.
*
* According to the mode selected, Sensor Subsystem Timers can be disabled.
*
* @param[in] mode Mode selection for SS1 state.
*/
//void ss_power_cpu_ss1(const ss_power_cpu_ss1_mode_t mode);
/**
* Enter Sensor SS2 state or SoC LPSS state.
*
* Put the Sensor Subsystem into SS2.<BR>
* Sensor Complex Clock is gated in this state.<BR>
* Sensor Peripherals are gated in this state.<BR>
*
* This enables entry in LPSS if:
* - Sensor Subsystem is in SS2
* - Lakemont is in C2 or C2LP
* - LPSS entry is enabled
*
* A wake event causes the Sensor Subsystem to transition to SS0.<BR>
* There are two kinds of wake event depending on the Sensor Subsystem
* and SoC state:
* - SS2: a wake event is a Sensor Subsystem interrupt
* - LPSS: a wake event is a Sensor Subsystem interrupt or a Lakemont interrupt
*
* LPSS wake events apply if LPSS is entered.
* If Host wakes the SoC from LPSS,
* Sensor also transitions back to SS0.
*/
//void ss_power_cpu_ss2(void);
/**
* Save resume vector.
*
* Saves the resume vector in the global "arc_restore_addr" location.
* The ARC will jump to the resume vector once a wake up event is
* triggered and x86 resumes the ARC.
*/
#define qm_ss_set_resume_vector(_restore_label, arc_restore_addr) \
__asm__ __volatile__("mov r0, @arc_restore_addr\n\t" \
"st " #_restore_label ", [r0]\n\t" \
: /* Output operands. */ \
: /* Input operands. */ \
: /* Clobbered registers list. */ \
"r0")
/* Save execution context.
*
* This routine saves CPU registers onto cpu_context,
* array.
*
*/
#define qm_ss_save_context(cpu_context) \
__asm__ __volatile__("push_s r0\n\t" \
"mov r0, @cpu_context\n\t" \
"st r1, [r0, 4]\n\t" \
"st r2, [r0, 8]\n\t" \
"st r3, [r0, 12]\n\t" \
"st r4, [r0, 16]\n\t" \
"st r5, [r0, 20]\n\t" \
"st r6, [r0, 24]\n\t" \
"st r7, [r0, 28]\n\t" \
"st r8, [r0, 32]\n\t" \
"st r9, [r0, 36]\n\t" \
"st r10, [r0, 40]\n\t" \
"st r11, [r0, 44]\n\t" \
"st r12, [r0, 48]\n\t" \
"st r13, [r0, 52]\n\t" \
"st r14, [r0, 56]\n\t" \
"st r15, [r0, 60]\n\t" \
"st r16, [r0, 64]\n\t" \
"st r17, [r0, 68]\n\t" \
"st r18, [r0, 72]\n\t" \
"st r19, [r0, 76]\n\t" \
"st r20, [r0, 80]\n\t" \
"st r21, [r0, 84]\n\t" \
"st r22, [r0, 88]\n\t" \
"st r23, [r0, 92]\n\t" \
"st r24, [r0, 96]\n\t" \
"st r25, [r0, 100]\n\t" \
"st r26, [r0, 104]\n\t" \
"st r27, [r0, 108]\n\t" \
"st r28, [r0, 112]\n\t" \
"st r29, [r0, 116]\n\t" \
"st r30, [r0, 120]\n\t" \
"st r31, [r0, 124]\n\t" \
"lr r31, [ic_ctrl]\n\t" \
"st r31, [r0, 128]\n\t" \
: /* Output operands. */ \
: /* Input operands. */ \
[ic_ctrl] "i"(QM_SS_AUX_IC_CTRL) \
: /* Clobbered registers list. */ \
"r0")
/* Restore execution context.
*
* This routine restores CPU registers from cpu_context,
* array.
*
* This routine is called from the bootloader to restore the execution context
* from before entering in sleep mode.
*/
#define qm_ss_restore_context(_restore_label, cpu_context) \
__asm__ __volatile__( \
#_restore_label \
":\n\t" \
"mov r0, @cpu_context\n\t" \
"ld r1, [r0, 4]\n\t" \
"ld r2, [r0, 8]\n\t" \
"ld r3, [r0, 12]\n\t" \
"ld r4, [r0, 16]\n\t" \
"ld r5, [r0, 20]\n\t" \
"ld r6, [r0, 24]\n\t" \
"ld r7, [r0, 28]\n\t" \
"ld r8, [r0, 32]\n\t" \
"ld r9, [r0, 36]\n\t" \
"ld r10, [r0, 40]\n\t" \
"ld r11, [r0, 44]\n\t" \
"ld r12, [r0, 48]\n\t" \
"ld r13, [r0, 52]\n\t" \
"ld r14, [r0, 56]\n\t" \
"ld r15, [r0, 60]\n\t" \
"ld r16, [r0, 64]\n\t" \
"ld r17, [r0, 68]\n\t" \
"ld r18, [r0, 72]\n\t" \
"ld r19, [r0, 76]\n\t" \
"ld r20, [r0, 80]\n\t" \
"ld r21, [r0, 84]\n\t" \
"ld r22, [r0, 88]\n\t" \
"ld r23, [r0, 92]\n\t" \
"ld r24, [r0, 96]\n\t" \
"ld r25, [r0, 100]\n\t" \
"ld r26, [r0, 104]\n\t" \
"ld r27, [r0, 108]\n\t" \
"ld r28, [r0, 112]\n\t" \
"ld r29, [r0, 116]\n\t" \
"ld r30, [r0, 120]\n\t" \
"ld r31, [r0, 124]\n\t" \
"ld r0, [r0, 128]\n\t" \
"sr r0, [ic_ctrl]\n\t" \
"pop_s r0\n\t" \
"sr 0,[0x101]\n\t" /* Setup Sensor Subsystem TimeStamp Counter */ \
"sr 0,[0x100]\n\t" \
"sr -1,[0x102]\n\t" \
: /* Output operands. */ \
: /* Input operands. */ \
[ic_ctrl] "i"(QM_SS_AUX_IC_CTRL) \
: /* Clobbered registers list. */ \
"r0")
/**
* @}
*/
#endif /* __QM_SS_POWER_STATES_H__ */