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libcontainer: intelrdt: add test cases for Intel RDT/MBA

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Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
This commit is contained in:
Xiaochen Shen
2018-10-16 12:38:00 +08:00
parent 1ed597bfe6
commit f097339289
2 changed files with 51 additions and 3 deletions
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14
libcontainer/container_linux_test.go
View File

@@ -148,6 +148,7 @@ func TestGetContainerStats(t *testing.T) {
intelRdtManager: &mockIntelRdtManager{ intelRdtManager: &mockIntelRdtManager{
stats: &intelrdt.Stats{ stats: &intelrdt.Stats{
L3CacheSchema: "L3:0=f;1=f0", L3CacheSchema: "L3:0=f;1=f0",
MemBwSchema: "MB:0=20;1=70",
}, },
}, },
} }
@@ -161,7 +162,7 @@ func TestGetContainerStats(t *testing.T) {
if stats.CgroupStats.MemoryStats.Usage.Usage != 1024 { if stats.CgroupStats.MemoryStats.Usage.Usage != 1024 {
t.Fatalf("expected memory usage 1024 but received %d", stats.CgroupStats.MemoryStats.Usage.Usage) t.Fatalf("expected memory usage 1024 but received %d", stats.CgroupStats.MemoryStats.Usage.Usage)
} }
if intelrdt.IsEnabled() { if intelrdt.IsCatEnabled() {
if stats.IntelRdtStats == nil { if stats.IntelRdtStats == nil {
t.Fatal("intel rdt stats are nil") t.Fatal("intel rdt stats are nil")
} }
@@ -169,6 +170,14 @@ func TestGetContainerStats(t *testing.T) {
t.Fatalf("expected L3CacheSchema L3:0=f;1=f0 but recevied %s", stats.IntelRdtStats.L3CacheSchema) t.Fatalf("expected L3CacheSchema L3:0=f;1=f0 but recevied %s", stats.IntelRdtStats.L3CacheSchema)
} }
} }
if intelrdt.IsMbaEnabled() {
if stats.IntelRdtStats == nil {
t.Fatal("intel rdt stats are nil")
}
if stats.IntelRdtStats.MemBwSchema != "MB:0=20;1=70" {
t.Fatalf("expected MemBwSchema MB:0=20;1=70 but recevied %s", stats.IntelRdtStats.MemBwSchema)
}
}
} }
func TestGetContainerState(t *testing.T) { func TestGetContainerState(t *testing.T) {
@@ -210,6 +219,7 @@ func TestGetContainerState(t *testing.T) {
intelRdtManager: &mockIntelRdtManager{ intelRdtManager: &mockIntelRdtManager{
stats: &intelrdt.Stats{ stats: &intelrdt.Stats{
L3CacheSchema: "L3:0=f0;1=f", L3CacheSchema: "L3:0=f0;1=f",
MemBwSchema: "MB:0=70;1=20",
}, },
path: expectedIntelRdtPath, path: expectedIntelRdtPath,
}, },
@@ -232,7 +242,7 @@ func TestGetContainerState(t *testing.T) {
if memPath := paths["memory"]; memPath != expectedMemoryPath { if memPath := paths["memory"]; memPath != expectedMemoryPath {
t.Fatalf("expected memory path %q but received %q", expectedMemoryPath, memPath) t.Fatalf("expected memory path %q but received %q", expectedMemoryPath, memPath)
} }
if intelrdt.IsEnabled() { if intelrdt.IsCatEnabled() || intelrdt.IsMbaEnabled() {
intelRdtPath := state.IntelRdtPath intelRdtPath := state.IntelRdtPath
if intelRdtPath == "" { if intelRdtPath == "" {
t.Fatal("intel rdt path should not be empty") t.Fatal("intel rdt path should not be empty")

40
libcontainer/intelrdt/intelrdt_test.go
View File

@@ -8,7 +8,7 @@ import (
) )
func TestIntelRdtSetL3CacheSchema(t *testing.T) { func TestIntelRdtSetL3CacheSchema(t *testing.T) {
if !IsEnabled() { if !IsCatEnabled() {
return return
} }
@@ -44,3 +44,41 @@ func TestIntelRdtSetL3CacheSchema(t *testing.T) {
t.Fatal("Got the wrong value, set 'schemata' failed.") t.Fatal("Got the wrong value, set 'schemata' failed.")
} }
} }
func TestIntelRdtSetMemBwSchema(t *testing.T) {
if !IsMbaEnabled() {
return
}
helper := NewIntelRdtTestUtil(t)
defer helper.cleanup()
const (
memBwSchemaBefore = "MB:0=20;1=70"
memBwSchemeAfter = "MB:0=70;1=20"
)
helper.writeFileContents(map[string]string{
"schemata": memBwSchemaBefore + "\n",
})
helper.IntelRdtData.config.IntelRdt.MemBwSchema = memBwSchemeAfter
intelrdt := &IntelRdtManager{
Config: helper.IntelRdtData.config,
Path: helper.IntelRdtPath,
}
if err := intelrdt.Set(helper.IntelRdtData.config); err != nil {
t.Fatal(err)
}
tmpStrings, err := getIntelRdtParamString(helper.IntelRdtPath, "schemata")
if err != nil {
t.Fatalf("Failed to parse file 'schemata' - %s", err)
}
values := strings.Split(tmpStrings, "\n")
value := values[0]
if value != memBwSchemeAfter {
t.Fatal("Got the wrong value, set 'schemata' failed.")
}
}