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Add a note about processor memory reordering

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Signed-off-by: Gilles Peskine <Gilles.Peskine@arm.com>
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Gilles Peskine
2025-06-12 18:30:45 +02:00
parent f5db3e9436
commit 853cfbdced
1 changed files with 7 additions and 0 deletions
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7
library/aesni.c
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@ -51,6 +51,13 @@ int mbedtls_aesni_has_support(unsigned int what)
/* To avoid a race condition, tell the compiler that the assignment /* To avoid a race condition, tell the compiler that the assignment
* `done = 1` and the assignment to `c` may not be reordered. * `done = 1` and the assignment to `c` may not be reordered.
* https://github.com/Mbed-TLS/mbedtls/issues/9840 * https://github.com/Mbed-TLS/mbedtls/issues/9840
*
* Note that we may also be worried about memory access reordering,
* but fortunately the x86 memory model is not too wild: stores
* from the same thread are observed consistently by other threads.
* (See example 8-1 in Sewell et al., "x86-TSO: A Rigorous and Usable
* Programmer’s Model for x86 Multiprocessors", CACM, 2010,
* https://www.cl.cam.ac.uk/~pes20/weakmemory/cacm.pdf)
*/ */
static volatile int done = 0; static volatile int done = 0;
static volatile unsigned int c = 0; static volatile unsigned int c = 0;