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The 53807741fb added a configure check
for 64-bit atomic operations that were not previously enabled on some
32-bit ABIs.
However, the NPTL semaphore code casts a sem_t to a new_sem and issues
a 64-bit atomic operation for __HAVE_64B_ATOMICS. Since sem_t has
32-bit alignment on 32-bit architectures, this prevents the use of
64-bit atomics even if the ABI supports them.
Assume 64-bit atomic support from __WORDSIZE, which maps to how glibc
defines it before the broken change. Also rename __HAVE_64B_ATOMICS
to USE_64B_ATOMICS to define better the flag meaning.
Checked on x86_64-linux-gnu and i686-linux-gnu.
Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
38 lines
1.4 KiB
C
38 lines
1.4 KiB
C
/* Atomic operations. Sparc version.
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Copyright (C) 2019-2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _SPARC_ATOMIC_MACHINE_H
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#define _SPARC_ATOMIC_MACHINE_H 1
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#include_next <atomic-machine.h>
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#ifdef __sparc_v9__
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# define atomic_full_barrier() \
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__asm __volatile ("membar #LoadLoad | #LoadStore" \
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" | #StoreLoad | #StoreStore" : : : "memory")
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# define atomic_read_barrier() \
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__asm __volatile ("membar #LoadLoad | #LoadStore" : : : "memory")
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# define atomic_write_barrier() \
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__asm __volatile ("membar #LoadStore | #StoreStore" : : : "memory")
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extern void __cpu_relax (void);
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# define atomic_spin_nop() __cpu_relax ()
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#endif
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#endif /* _ATOMIC_MACHINE_H */
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