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POWER ISA 3.0 introduces the xssqrtqp instructions, which expects operands to be in Vector Registers (Altivec/VMX), even though this instruction belongs to the Vector-Scalar Instruction Set. In GCC's Extended Assembly for POWER, the 'wq' register constraint is provided for use with IEEE 754 128-bit floating-point values. However, this constraint does not limit the register allocation to Vector Registers (Altivec/VMX) and could assign a Vector-Scalar Register (VSX) to the operands of the instruction. This patch changes the register constraint used in sqrtf128 from 'wq' to 'v', in order to request a Vector Register (Altivec/VMX) for use with the xssqrtqp instruction. Tested for powerpc64le and --with-cpu=power9. [BZ #21941] * sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since xssqrtqp requires operands to be in Vector Registers (Altivec/VMX), replace the register constraint 'wq' with 'v'. * sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c (__ieee754_sqrtf128): Likewise.
153 lines
3.2 KiB
C
153 lines
3.2 KiB
C
/* Private inline math functions for powerpc.
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Copyright (C) 2006-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _PPC_MATH_PRIVATE_H_
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#define _PPC_MATH_PRIVATE_H_
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#include <sysdep.h>
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#include <ldsodefs.h>
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#include <dl-procinfo.h>
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#include <fenv_private.h>
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#include_next <math_private.h>
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#if defined _ARCH_PWR9 && __HAVE_DISTINCT_FLOAT128
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extern __always_inline _Float128
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__ieee754_sqrtf128 (_Float128 __x)
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{
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_Float128 __z;
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asm ("xssqrtqp %0,%1" : "=v" (__z) : "v" (__x));
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return __z;
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}
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#endif
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extern double __slow_ieee754_sqrt (double);
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extern __always_inline double
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__ieee754_sqrt (double __x)
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{
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double __z;
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#ifdef _ARCH_PPCSQ
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asm ("fsqrt %0,%1" : "=f" (__z) : "f" (__x));
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#else
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__z = __slow_ieee754_sqrt(__x);
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#endif
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return __z;
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}
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extern float __slow_ieee754_sqrtf (float);
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extern __always_inline float
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__ieee754_sqrtf (float __x)
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{
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float __z;
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#ifdef _ARCH_PPCSQ
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asm ("fsqrts %0,%1" : "=f" (__z) : "f" (__x));
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#else
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__z = __slow_ieee754_sqrtf(__x);
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#endif
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return __z;
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}
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#if defined _ARCH_PWR5X
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# ifndef __round
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# define __round(x) \
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({ double __z; \
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__asm __volatile ( \
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" frin %0,%1\n" \
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: "=f" (__z) \
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: "f" (x)); \
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__z; })
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# endif
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# ifndef __roundf
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# define __roundf(x) \
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({ float __z; \
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__asm __volatile ( \
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" frin %0,%1\n" \
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" frsp %0,%0\n" \
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: "=f" (__z) \
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: "f" (x)); \
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__z; })
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# endif
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# ifndef __trunc
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# define __trunc(x) \
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({ double __z; \
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__asm __volatile ( \
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" friz %0,%1\n" \
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: "=f" (__z) \
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: "f" (x)); \
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__z; })
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# endif
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# ifndef __truncf
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# define __truncf(x) \
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({ float __z; \
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__asm __volatile ( \
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" friz %0,%1\n" \
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" frsp %0,%0\n" \
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: "=f" (__z) \
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: "f" (x)); \
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__z; })
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# endif
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# ifndef __ceil
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# define __ceil(x) \
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({ double __z; \
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__asm __volatile ( \
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" frip %0,%1\n" \
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: "=f" (__z) \
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: "f" (x)); \
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__z; })
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# endif
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# ifndef __ceilf
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# define __ceilf(x) \
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({ float __z; \
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__asm __volatile ( \
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" frip %0,%1\n" \
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" frsp %0,%0\n" \
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: "=f" (__z) \
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: "f" (x)); \
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__z; })
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# endif
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# ifndef __floor
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# define __floor(x) \
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({ double __z; \
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__asm __volatile ( \
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" frim %0,%1\n" \
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: "=f" (__z) \
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: "f" (x)); \
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__z; })
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# endif
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# ifndef __floorf
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# define __floorf(x) \
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({ float __z; \
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__asm __volatile ( \
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" frim %0,%1\n" \
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" frsp %0,%0\n" \
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: "=f" (__z) \
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: "f" (x)); \
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__z; })
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# endif
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#endif /* defined _ARCH_PWR5X */
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#endif /* _PPC_MATH_PRIVATE_H_ */
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