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8cd6efca5b
To enable “longlong.h” removal, add_ssaaaa and sub_ssaaaa are moved to gmp-arch.h. The generic implementation now uses a static inline. This provides better type checking than the GNU extension, which casts the asm constraint; and it also works better with clang. Most architectures use the generic implementation, with except of arc, arm, hppa, x86, m68k, powerpc, and sparc. The 32 bit architectures the compiler generates good enough code using uint64_t types, where for 64 bit architecture the patch leverages the math_u128.h definitions that uses 128-bit integers when available (all 64 bit architectures on gcc 15). The strongly typed implementation required some changes. I adjusted _FP_W_TYPE, _FP_WS_TYPE, and _FP_I_TYPE to use the same type as mp_limb_t on aarch64, powerpc64le, x86_64, and riscv64. This basically means using “long” instead of “long long.” Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
226 lines
6.7 KiB
C
226 lines
6.7 KiB
C
/* Configure soft-fp for building sqrtf128. Based on sfp-machine.h in
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libgcc, with soft-float and other irrelevant parts removed. */
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#include <math-inline-asm.h>
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#if HAVE_X86_LIBGCC_CMP_RETURN_ATTR
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/* The type of the result of a floating point comparison. This must
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match `__libgcc_cmp_return__' in GCC for the target. */
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typedef int __gcc_CMPtype_GCC __attribute__ ((mode (__libgcc_cmp_return__)));
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#else
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# ifdef __x86_64__
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typedef long long int __gcc_CMPtype;
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#else
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typedef long int __gcc_CMPtype;
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# endif
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#endif
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#define CMPtype __gcc_CMPtype
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#ifdef __x86_64__
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# define _FP_W_TYPE_SIZE 64
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# ifndef __ILP32__
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# define _FP_W_TYPE unsigned long
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# define _FP_WS_TYPE signed long
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# define _FP_I_TYPE long
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# else
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# define _FP_W_TYPE unsigned long long
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# define _FP_WS_TYPE signed long long
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# define _FP_I_TYPE long long
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# endif
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typedef int TItype __attribute__ ((mode (TI)));
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typedef unsigned int UTItype __attribute__ ((mode (TI)));
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# define TI_BITS (__CHAR_BIT__ * (int) sizeof (TItype))
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# define _FP_MUL_MEAT_Q(R,X,Y) \
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_FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
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# define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
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# define _FP_NANFRAC_S _FP_QNANBIT_S
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# define _FP_NANFRAC_D _FP_QNANBIT_D
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# define _FP_NANFRAC_E _FP_QNANBIT_E, 0
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# define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0
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# define FP_EX_SHIFT 7
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# define _FP_DECL_EX \
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unsigned int _fcw __attribute__ ((unused)) = FP_RND_NEAREST;
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# define FP_RND_NEAREST 0
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# define FP_RND_ZERO 0x6000
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# define FP_RND_PINF 0x4000
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# define FP_RND_MINF 0x2000
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# define FP_RND_MASK 0x6000
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# define FP_INIT_ROUNDMODE \
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do { \
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stmxcsr_inline_asm (&_fcw); \
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} while (0)
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#else
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# define _FP_W_TYPE_SIZE 32
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# define _FP_W_TYPE unsigned long int
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# define _FP_WS_TYPE signed long int
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# define _FP_I_TYPE long int
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# define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
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__asm__ ("add{l} {%11,%3|%3,%11}\n\t" \
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"adc{l} {%9,%2|%2,%9}\n\t" \
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"adc{l} {%7,%1|%1,%7}\n\t" \
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"adc{l} {%5,%0|%0,%5}" \
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: "=r" ((USItype) (r3)), \
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"=&r" ((USItype) (r2)), \
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"=&r" ((USItype) (r1)), \
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"=&r" ((USItype) (r0)) \
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: "%0" ((USItype) (x3)), \
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"g" ((USItype) (y3)), \
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"%1" ((USItype) (x2)), \
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"g" ((USItype) (y2)), \
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"%2" ((USItype) (x1)), \
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"g" ((USItype) (y1)), \
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"%3" ((USItype) (x0)), \
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"g" ((USItype) (y0)))
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# define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
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__asm__ ("add{l} {%8,%2|%2,%8}\n\t" \
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"adc{l} {%6,%1|%1,%6}\n\t" \
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"adc{l} {%4,%0|%0,%4}" \
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: "=r" ((USItype) (r2)), \
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"=&r" ((USItype) (r1)), \
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"=&r" ((USItype) (r0)) \
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: "%0" ((USItype) (x2)), \
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"g" ((USItype) (y2)), \
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"%1" ((USItype) (x1)), \
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"g" ((USItype) (y1)), \
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"%2" ((USItype) (x0)), \
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"g" ((USItype) (y0)))
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# define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
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__asm__ ("sub{l} {%11,%3|%3,%11}\n\t" \
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"sbb{l} {%9,%2|%2,%9}\n\t" \
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"sbb{l} {%7,%1|%1,%7}\n\t" \
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"sbb{l} {%5,%0|%0,%5}" \
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: "=r" ((USItype) (r3)), \
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"=&r" ((USItype) (r2)), \
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"=&r" ((USItype) (r1)), \
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"=&r" ((USItype) (r0)) \
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: "0" ((USItype) (x3)), \
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"g" ((USItype) (y3)), \
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"1" ((USItype) (x2)), \
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"g" ((USItype) (y2)), \
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"2" ((USItype) (x1)), \
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"g" ((USItype) (y1)), \
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"3" ((USItype) (x0)), \
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"g" ((USItype) (y0)))
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# define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
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__asm__ ("sub{l} {%8,%2|%2,%8}\n\t" \
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"sbb{l} {%6,%1|%1,%6}\n\t" \
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"sbb{l} {%4,%0|%0,%4}" \
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: "=r" ((USItype) (r2)), \
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"=&r" ((USItype) (r1)), \
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"=&r" ((USItype) (r0)) \
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: "0" ((USItype) (x2)), \
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"g" ((USItype) (y2)), \
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"1" ((USItype) (x1)), \
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"g" ((USItype) (y1)), \
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"2" ((USItype) (x0)), \
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"g" ((USItype) (y0)))
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# define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \
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__asm__ ("add{l} {%4,%3|%3,%4}\n\t" \
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"adc{l} {$0,%2|%2,0}\n\t" \
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"adc{l} {$0,%1|%1,0}\n\t" \
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"adc{l} {$0,%0|%0,0}" \
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: "+r" ((USItype) (x3)), \
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"+&r" ((USItype) (x2)), \
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"+&r" ((USItype) (x1)), \
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"+&r" ((USItype) (x0)) \
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: "g" ((USItype) (i)))
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# define _FP_MUL_MEAT_S(R,X,Y) \
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_FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
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# define _FP_MUL_MEAT_D(R,X,Y) \
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_FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
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# define _FP_MUL_MEAT_Q(R,X,Y) \
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_FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
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# define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y)
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# define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
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# define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
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# define _FP_NANFRAC_S _FP_QNANBIT_S
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# define _FP_NANFRAC_D _FP_QNANBIT_D, 0
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/* Even if XFmode is 12byte, we have to pad it to
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16byte since soft-fp emulation is done in 16byte. */
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# define _FP_NANFRAC_E _FP_QNANBIT_E, 0, 0, 0
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# define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0
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# define FP_EX_SHIFT 0
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# define _FP_DECL_EX \
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unsigned short _fcw __attribute__ ((unused)) = FP_RND_NEAREST;
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# define FP_RND_NEAREST 0
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# define FP_RND_ZERO 0xc00
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# define FP_RND_PINF 0x800
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# define FP_RND_MINF 0x400
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# define FP_RND_MASK 0xc00
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# define FP_INIT_ROUNDMODE \
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do { \
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__asm__ __volatile__ ("fnstcw\t%0" : "=m" (_fcw)); \
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} while (0)
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#endif
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#define _FP_KEEPNANFRACP 1
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#define _FP_QNANNEGATEDP 0
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#define _FP_NANSIGN_S 1
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#define _FP_NANSIGN_D 1
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#define _FP_NANSIGN_E 1
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#define _FP_NANSIGN_Q 1
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/* Here is something Intel misdesigned: the specs don't define
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the case where we have two NaNs with same mantissas, but
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different sign. Different operations pick up different NaNs. */
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#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do { \
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if (_FP_FRAC_GT_##wc(X, Y) \
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|| (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
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{ \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc(R,X); \
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} \
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else \
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{ \
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R##_s = Y##_s; \
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_FP_FRAC_COPY_##wc(R,Y); \
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} \
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R##_c = FP_CLS_NAN; \
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} while (0)
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#define FP_EX_INVALID 0x01
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#define FP_EX_DENORM 0x02
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#define FP_EX_DIVZERO 0x04
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#define FP_EX_OVERFLOW 0x08
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#define FP_EX_UNDERFLOW 0x10
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#define FP_EX_INEXACT 0x20
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#define FP_EX_ALL \
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(FP_EX_INVALID | FP_EX_DENORM | FP_EX_DIVZERO | FP_EX_OVERFLOW \
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| FP_EX_UNDERFLOW | FP_EX_INEXACT)
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void __sfp_handle_exceptions (int);
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#define FP_HANDLE_EXCEPTIONS \
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do { \
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if (__builtin_expect (_fex, 0)) \
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__sfp_handle_exceptions (_fex); \
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} while (0);
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#define FP_TRAPPING_EXCEPTIONS ((~_fcw >> FP_EX_SHIFT) & FP_EX_ALL)
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#define FP_ROUNDMODE (_fcw & FP_RND_MASK)
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#define _FP_TININESS_AFTER_ROUNDING 1
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