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7fec8a5de6
The 53807741fb added a configure check
for 64-bit atomic operations that were not previously enabled on some
32-bit ABIs.
However, the NPTL semaphore code casts a sem_t to a new_sem and issues
a 64-bit atomic operation for __HAVE_64B_ATOMICS. Since sem_t has
32-bit alignment on 32-bit architectures, this prevents the use of
64-bit atomics even if the ABI supports them.
Assume 64-bit atomic support from __WORDSIZE, which maps to how glibc
defines it before the broken change. Also rename __HAVE_64B_ATOMICS
to USE_64B_ATOMICS to define better the flag meaning.
Checked on x86_64-linux-gnu and i686-linux-gnu.
Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
54 lines
1.9 KiB
C
54 lines
1.9 KiB
C
/* Low-level functions for atomic operations. RISC-V version.
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Copyright (C) 2014-2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _LINUX_RISCV_BITS_ATOMIC_H
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#define _LINUX_RISCV_BITS_ATOMIC_H 1
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#ifdef __riscv_atomic
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#include_next <atomic-machine.h>
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/* Miscellaneous. */
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# define asm_amo(which, ordering, mem, value) ({ \
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__atomic_check_size (mem); \
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typeof (*mem) __tmp; \
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if (sizeof (__tmp) == 4) \
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asm volatile (which ".w" ordering "\t%0, %z2, %1" \
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: "=r" (__tmp), "+A" (* (mem)) \
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: "rJ" (value)); \
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else if (sizeof (__tmp) == 8) \
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asm volatile (which ".d" ordering "\t%0, %z2, %1" \
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: "=r" (__tmp), "+A" (* (mem)) \
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: "rJ" (value)); \
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else \
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abort (); \
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__tmp; })
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# define atomic_max(mem, value) asm_amo ("amomaxu", ".aq", mem, value)
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# define atomic_min(mem, value) asm_amo ("amominu", ".aq", mem, value)
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#else /* __riscv_atomic */
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# error "ISAs that do not subsume the A extension are not supported"
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#endif /* !__riscv_atomic */
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/* Execute a PAUSE hint when spinning. */
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#define atomic_spin_nop() __asm(".insn i 0x0f, 0, x0, x0, 0x010")
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#endif /* bits/atomic.h */
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