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324c088a18
The only usage was for pthread_spin_lock, introduced by 12d2dd7060,
as a way to optimize the code for certain architectures. Now that atomic
builtins are used by default, let the compiler use the best code sequence
for the atomic exchange.
Co-authored-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/* Copyright (C) 2003-2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include "pthreadP.h"
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#include <shlib-compat.h>
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#define __ARCH_ACQ_INSTR "isync"
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#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
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# define MUTEX_HINT_ACQ ",1"
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# define MUTEX_HINT_REL ",0"
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#else
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# define MUTEX_HINT_ACQ
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# define MUTEX_HINT_REL
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#endif
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int
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__pthread_spin_lock (pthread_spinlock_t *lock)
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{
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unsigned int __tmp;
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asm volatile (
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"1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n"
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" cmpwi 0,%0,0\n"
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" bne- 2f\n"
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" stwcx. %2,0,%1\n"
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" bne- 2f\n"
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__ARCH_ACQ_INSTR "\n"
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" .subsection 1\n"
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"2: lwzx %0,0,%1\n"
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" cmpwi 0,%0,0\n"
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" bne 2b\n"
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" b 1b\n"
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" .previous"
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: "=&r" (__tmp)
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: "r" (lock), "r" (1)
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: "cr0", "memory");
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return 0;
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}
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versioned_symbol (libc, __pthread_spin_lock, pthread_spin_lock, GLIBC_2_34);
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#if OTHER_SHLIB_COMPAT (libpthread, GLIBC_2_2, GLIBC_2_34)
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compat_symbol (libpthread, __pthread_spin_lock, pthread_spin_lock, GLIBC_2_2);
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#endif
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