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388 lines
13 KiB
C
388 lines
13 KiB
C
/* Assembler macros for ARM.
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Copyright (C) 1997-2015 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdeps/generic/sysdep.h>
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#include <features.h>
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#ifndef __ASSEMBLER__
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# include <stdint.h>
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#else
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# include <arm-features.h>
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#endif
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/* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */
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#ifndef __ARM_ARCH
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# ifdef __ARM_ARCH_2__
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# define __ARM_ARCH 2
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# elif defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__)
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# define __ARM_ARCH 3
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# elif defined (__ARM_ARCH_4__) || defined (__ARM_ARCH_4T__)
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# define __ARM_ARCH 4
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# elif defined (__ARM_ARCH_5__) || defined (__ARM_ARCH_5E__) \
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|| defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
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|| defined(__ARM_ARCH_5TEJ__)
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# define __ARM_ARCH 5
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# elif defined (__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
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|| defined (__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
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|| defined (__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
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# define __ARM_ARCH 6
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# elif defined (__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
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|| defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
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|| defined(__ARM_ARCH_7EM__)
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# define __ARM_ARCH 7
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# else
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# error unknown arm architecture
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# endif
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#endif
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#if __ARM_ARCH > 4 || defined (__ARM_ARCH_4T__)
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# define ARCH_HAS_BX
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#endif
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#if __ARM_ARCH > 4
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# define ARCH_HAS_BLX
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#endif
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#if __ARM_ARCH > 6 || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__)
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# define ARCH_HAS_HARD_TP
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#endif
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#if __ARM_ARCH > 6 || defined (__ARM_ARCH_6T2__)
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# define ARCH_HAS_T2
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#endif
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#ifdef __ASSEMBLER__
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/* Syntactic details of assembler. */
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#define ALIGNARG(log2) log2
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#define ASM_SIZE_DIRECTIVE(name) .size name,.-name
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#define PLTJMP(_x) _x##(PLT)
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#ifdef ARCH_HAS_BX
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# define BX(R) bx R
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# define BXC(C, R) bx##C R
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# ifdef ARCH_HAS_BLX
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# define BLX(R) blx R
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# else
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# define BLX(R) mov lr, pc; bx R
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# endif
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#else
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# define BX(R) mov pc, R
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# define BXC(C, R) mov##C pc, R
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# define BLX(R) mov lr, pc; mov pc, R
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#endif
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#define DO_RET(R) BX(R)
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#define RETINSTR(C, R) BXC(C, R)
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/* Define an entry point visible from C. */
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#define ENTRY(name) \
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.globl C_SYMBOL_NAME(name); \
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.type C_SYMBOL_NAME(name),%function; \
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.align ALIGNARG(4); \
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C_LABEL(name) \
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CFI_SECTIONS; \
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cfi_startproc; \
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CALL_MCOUNT
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#define CFI_SECTIONS \
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.cfi_sections .debug_frame
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#undef END
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#define END(name) \
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cfi_endproc; \
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ASM_SIZE_DIRECTIVE(name)
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/* If compiled for profiling, call `mcount' at the start of each function. */
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#ifdef PROF
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/* Call __gnu_mcount_nc (GCC >= 4.4). */
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#define CALL_MCOUNT \
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push {lr}; \
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cfi_adjust_cfa_offset (4); \
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cfi_rel_offset (lr, 0); \
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bl PLTJMP(mcount); \
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cfi_adjust_cfa_offset (-4); \
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cfi_restore (lr)
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#else
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#define CALL_MCOUNT /* Do nothing. */
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#endif
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/* Since C identifiers are not normally prefixed with an underscore
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on this system, the asm identifier `syscall_error' intrudes on the
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C name space. Make sure we use an innocuous name. */
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#define syscall_error __syscall_error
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#define mcount __gnu_mcount_nc
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/* Tag_ABI_align8_preserved: This code preserves 8-byte
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alignment in any callee. */
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.eabi_attribute 25, 1
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/* Tag_ABI_align8_needed: This code may require 8-byte alignment from
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the caller. */
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.eabi_attribute 24, 1
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/* The thumb2 encoding is reasonably complete. Unless suppressed, use it. */
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.syntax unified
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# if defined(__thumb2__) && !defined(NO_THUMB)
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.thumb
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#else
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# undef __thumb__
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# undef __thumb2__
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.arm
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# endif
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/* Load or store to/from address X + Y into/from R, (maybe) using T.
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X or Y can use T freely; T can be R if OP is a load. The first
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version eschews the two-register addressing mode, while the
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second version uses it. */
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# define LDST_INDEXED_NOINDEX(OP, R, T, X, Y) \
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add T, X, Y; \
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sfi_breg T, \
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OP R, [T]
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# define LDST_INDEXED_INDEX(OP, R, X, Y) \
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OP R, [X, Y]
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# ifdef ARM_NO_INDEX_REGISTER
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/* We're never using the two-register addressing mode, so this
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always uses an intermediate add. */
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# define LDST_INDEXED(OP, R, T, X, Y) LDST_INDEXED_NOINDEX (OP, R, T, X, Y)
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# define LDST_PC_INDEXED(OP, R, T, X) LDST_INDEXED_NOINDEX (OP, R, T, pc, X)
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# else
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/* The two-register addressing mode is OK, except on Thumb with pc. */
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# define LDST_INDEXED(OP, R, T, X, Y) LDST_INDEXED_INDEX (OP, R, X, Y)
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# ifdef __thumb2__
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# define LDST_PC_INDEXED(OP, R, T, X) LDST_INDEXED_NOINDEX (OP, R, T, pc, X)
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# else
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# define LDST_PC_INDEXED(OP, R, T, X) LDST_INDEXED_INDEX (OP, R, pc, X)
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# endif
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# endif
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/* Load or store to/from a pc-relative EXPR into/from R, using T. */
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# ifdef __thumb2__
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# define LDST_PCREL(OP, R, T, EXPR) \
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ldr T, 98f; \
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.subsection 2; \
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98: .word EXPR - 99f - PC_OFS; \
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.previous; \
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99: add T, T, pc; \
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OP R, [T]
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# elif defined (ARCH_HAS_T2) && ARM_PCREL_MOVW_OK
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# define LDST_PCREL(OP, R, T, EXPR) \
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movw T, #:lower16:EXPR - 99f - PC_OFS; \
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movt T, #:upper16:EXPR - 99f - PC_OFS; \
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99: LDST_PC_INDEXED (OP, R, T, T)
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# else
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# define LDST_PCREL(OP, R, T, EXPR) \
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ldr T, 98f; \
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.subsection 2; \
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98: .word EXPR - 99f - PC_OFS; \
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.previous; \
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99: OP R, [pc, T]
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# endif
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/* Load from a global SYMBOL + CONSTANT into R, using T. */
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# if defined (ARCH_HAS_T2) && !defined (PIC)
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# define LDR_GLOBAL(R, T, SYMBOL, CONSTANT) \
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movw T, #:lower16:SYMBOL; \
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movt T, #:upper16:SYMBOL; \
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sfi_breg T, ldr R, [\B, $CONSTANT]
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# elif defined (ARCH_HAS_T2) && defined (PIC) && ARM_PCREL_MOVW_OK
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# define LDR_GLOBAL(R, T, SYMBOL, CONSTANT) \
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movw R, #:lower16:_GLOBAL_OFFSET_TABLE_ - 97f - PC_OFS; \
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movw T, #:lower16:99f - 98f - PC_OFS; \
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movt R, #:upper16:_GLOBAL_OFFSET_TABLE_ - 97f - PC_OFS; \
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movt T, #:upper16:99f - 98f - PC_OFS; \
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.pushsection .rodata.cst4, "aM", %progbits, 4; \
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.balign 4; \
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99: .word SYMBOL##(GOT); \
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.popsection; \
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97: add R, R, pc; \
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98: LDST_PC_INDEXED (ldr, T, T, T); \
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LDST_INDEXED (ldr, R, T, R, T); \
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sfi_breg R, ldr R, [\B, $CONSTANT]
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# else
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# define LDR_GLOBAL(R, T, SYMBOL, CONSTANT) \
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ldr T, 99f; \
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ldr R, 100f; \
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98: add T, T, pc; \
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ldr T, [T, R]; \
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.subsection 2; \
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99: .word _GLOBAL_OFFSET_TABLE_ - 98b - PC_OFS; \
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100: .word SYMBOL##(GOT); \
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.previous; \
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ldr R, [T, $CONSTANT]
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# endif
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/* This is the same as LDR_GLOBAL, but for a SYMBOL that is known to
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be in the same linked object (as for one with hidden visibility).
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We can avoid the GOT indirection in the PIC case. For the pure
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static case, LDR_GLOBAL is already optimal. */
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# ifdef PIC
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# define LDR_HIDDEN(R, T, SYMBOL, CONSTANT) \
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LDST_PCREL (ldr, R, T, SYMBOL + CONSTANT)
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# else
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# define LDR_HIDDEN(R, T, SYMBOL, CONSTANT) \
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LDR_GLOBAL (R, T, SYMBOL, CONSTANT)
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# endif
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/* Cope with negative memory offsets, which thumb can't encode.
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Use NEGOFF_ADJ_BASE to (conditionally) alter the base register,
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and then NEGOFF_OFF1 to use 0 for thumb and the offset for arm,
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or NEGOFF_OFF2 to use A-B for thumb and A for arm. */
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# ifdef __thumb2__
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# define NEGOFF_ADJ_BASE(R, OFF) add R, R, $OFF
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# define NEGOFF_ADJ_BASE2(D, S, OFF) add D, S, $OFF
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# define NEGOFF_OFF1(R, OFF) [R]
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# define NEGOFF_OFF2(R, OFFA, OFFB) [R, $((OFFA) - (OFFB))]
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# else
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# define NEGOFF_ADJ_BASE(R, OFF)
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# define NEGOFF_ADJ_BASE2(D, S, OFF) mov D, S
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# define NEGOFF_OFF1(R, OFF) [R, $OFF]
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# define NEGOFF_OFF2(R, OFFA, OFFB) [R, $OFFA]
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# endif
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/* Helper to get the TLS base pointer. The interface is that TMP is a
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register that may be used to hold the LR, if necessary. TMP may be
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LR itself to indicate that LR need not be saved. The base pointer
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is returned in R0. Only R0 and TMP are modified. */
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# ifdef ARCH_HAS_HARD_TP
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/* If the cpu has cp15 available, use it. */
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# define GET_TLS(TMP) mrc p15, 0, r0, c13, c0, 3
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# else
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/* At this generic level we have no tricks to pull. Call the ABI routine. */
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# define GET_TLS(TMP) \
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push { r1, r2, r3, lr }; \
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cfi_remember_state; \
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cfi_adjust_cfa_offset (16); \
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cfi_rel_offset (r1, 0); \
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cfi_rel_offset (r2, 4); \
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cfi_rel_offset (r3, 8); \
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cfi_rel_offset (lr, 12); \
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bl __aeabi_read_tp; \
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pop { r1, r2, r3, lr }; \
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cfi_restore_state
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# endif /* ARCH_HAS_HARD_TP */
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# ifndef ARM_SFI_MACROS
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# define ARM_SFI_MACROS 1
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/* This assembly macro is prepended to any load/store instruction,
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pulling the base register out of the addressing mode syntax and
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making it the first operand of the macro. For example:
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ldr r0, [r1]
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becomes:
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sfi_breg r1, ldr r0, [\B]
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The \B stands in for the base register that is the first operand
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to the macro, so we can avoid error-prone repetition of the base
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register in two places on the line.
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This is used for all memory access through a base register other
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than PC or SP. It's intended to support SFI schemes such as
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Native Client, where the OS will enforce that all load/store
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instructions use a special form. In any such configuration,
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another sysdep.h file will have defined ARM_SFI_MACROS and
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provided its own assembly macros with the same interface. */
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.macro sfi_breg basereg, insn, operands:vararg
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.macro _sfi_breg_doit B
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\insn \operands
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.endm
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_sfi_breg_doit \basereg
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.purgem _sfi_breg_doit
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.endm
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/* This assembly macro replaces the "pld" instruction.
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The syntax:
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sfi_pld REGISTER, #OFFSET
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is exactly equivalent to:
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sfi_breg REGISTER, pld [\B, #OFFSET]
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(and ", #OFFSET" is optional). We have a separate macro
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only to work around a bug in GAS versions prior to 2.23.2,
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that misparses the sfi_breg macro expansion in this case. */
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.macro sfi_pld basereg, offset=#0
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pld [\basereg, \offset]
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.endm
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/* This macro precedes any instruction that directly changes the SP.
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It's not needed for push/pop or for any kind of load or store that
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implicitly changes the SP via the ! syntax. */
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# define sfi_sp /* Nothing to do. */
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# endif
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/* These are the directives used for EABI unwind info.
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Wrap them in macros so another configuration's sysdep.h
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file can define them away if it doesn't use EABI unwind info. */
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# define eabi_fnstart .fnstart
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# define eabi_fnend .fnend
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# define eabi_save(...) .save __VA_ARGS__
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# define eabi_cantunwind .cantunwind
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# define eabi_pad(n) .pad n
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#endif /* __ASSEMBLER__ */
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/* This number is the offset from the pc at the current location. */
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#ifdef __thumb__
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# define PC_OFS 4
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#else
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# define PC_OFS 8
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#endif
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/* Pointer mangling support. */
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#if (IS_IN (rtld) || \
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(!defined SHARED && (IS_IN (libc) || IS_IN (libpthread))))
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# ifdef __ASSEMBLER__
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# define PTR_MANGLE_LOAD(guard, tmp) \
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LDR_HIDDEN (guard, tmp, C_SYMBOL_NAME(__pointer_chk_guard_local), 0)
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# define PTR_MANGLE(dst, src, guard, tmp) \
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PTR_MANGLE_LOAD(guard, tmp); \
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PTR_MANGLE2(dst, src, guard)
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/* Use PTR_MANGLE2 for efficiency if guard is already loaded. */
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# define PTR_MANGLE2(dst, src, guard) \
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eor dst, src, guard
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# define PTR_DEMANGLE(dst, src, guard, tmp) \
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PTR_MANGLE (dst, src, guard, tmp)
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# define PTR_DEMANGLE2(dst, src, guard) \
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PTR_MANGLE2 (dst, src, guard)
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# else
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extern uintptr_t __pointer_chk_guard_local attribute_relro attribute_hidden;
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# define PTR_MANGLE(var) \
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(var) = (__typeof (var)) ((uintptr_t) (var) ^ __pointer_chk_guard_local)
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# define PTR_DEMANGLE(var) PTR_MANGLE (var)
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# endif
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#else
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# ifdef __ASSEMBLER__
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# define PTR_MANGLE_LOAD(guard, tmp) \
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LDR_GLOBAL (guard, tmp, C_SYMBOL_NAME(__pointer_chk_guard), 0);
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# define PTR_MANGLE(dst, src, guard, tmp) \
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PTR_MANGLE_LOAD(guard, tmp); \
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PTR_MANGLE2(dst, src, guard)
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/* Use PTR_MANGLE2 for efficiency if guard is already loaded. */
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# define PTR_MANGLE2(dst, src, guard) \
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eor dst, src, guard
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# define PTR_DEMANGLE(dst, src, guard, tmp) \
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PTR_MANGLE (dst, src, guard, tmp)
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# define PTR_DEMANGLE2(dst, src, guard) \
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PTR_MANGLE2 (dst, src, guard)
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# else
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extern uintptr_t __pointer_chk_guard attribute_relro;
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# define PTR_MANGLE(var) \
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(var) = (__typeof (var)) ((uintptr_t) (var) ^ __pointer_chk_guard)
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# define PTR_DEMANGLE(var) PTR_MANGLE (var)
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# endif
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#endif
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