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bea5801360
GLIBC memset optimization for POWER8 uses the '.machine power8' directive, which is only supported officially on binutils 2.24+. This causes a build failure on older binutils. Since the requirement of .machine power8 is to correctly assembly the 'mtvsrd' instruction and it is already handled by the MTVSRD_V1_R4 macro, there is no really needed of using it. The patch replaces the power8 with power7 for .machine directive. It fixes BZ#17869.
455 lines
7.8 KiB
ArmAsm
455 lines
7.8 KiB
ArmAsm
/* Optimized memset implementation for PowerPC64/POWER8.
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Copyright (C) 2014-2015 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#define MTVSRD_V1_R4 .long 0x7c240166 /* mtvsrd v1,r4 */
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/* __ptr_t [r3] memset (__ptr_t s [r3], int c [r4], size_t n [r5]));
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Returns 's'. */
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/* No need to use .machine power8 since mtvsrd is already
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handled by the define. It avoid breakage on binutils
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that does not support this machine specifier. */
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.machine power7
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EALIGN (memset, 5, 0)
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CALL_MCOUNT 3
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L(_memset):
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cmpldi cr7,r5,31
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neg r0,r3
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mr r10,r3
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insrdi r4,r4,8,48
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insrdi r4,r4,16,32 /* Replicate byte to word. */
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ble cr7,L(write_LT_32)
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andi. r11,r10,15 /* Check alignment of DST. */
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insrdi r4,r4,32,0 /* Replicate word to double word. */
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beq L(big_aligned)
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mtocrf 0x01,r0
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clrldi r0,r0,60
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/* Get DST aligned to 16 bytes. */
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1: bf 31,2f
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stb r4,0(r10)
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addi r10,r10,1
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2: bf 30,4f
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sth r4,0(r10)
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addi r10,r10,2
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4: bf 29,8f
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stw r4,0(r10)
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addi r10,r10,4
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8: bf 28,16f
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std r4,0(r10)
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addi r10,r10,8
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16: subf r5,r0,r5
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.align 4
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L(big_aligned):
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/* For sizes larger than 255 two possible paths:
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- if constant is '0', zero full cache lines with dcbz
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- otherwise uses vector instructions. */
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cmpldi cr5,r5,255
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dcbtst 0,r10
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cmpldi cr6,r4,0
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crand 27,26,21
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bt 27,L(huge_dcbz)
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bge cr5,L(huge_vector)
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/* Size between 32 and 255 bytes with constant different than 0, use
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doubleword store instruction to achieve best throughput. */
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srdi r8,r5,5
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clrldi r11,r5,59
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cmpldi cr6,r11,0
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cmpdi r8,0
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beq L(tail_bytes)
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mtctr r8
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/* Main aligned write loop, writes 32-bytes at a time. */
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.align 4
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L(big_loop):
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std r4,0(r10)
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std r4,8(r10)
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std r4,16(r10)
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std r4,24(r10)
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addi r10,r10,32
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bdz L(tail_bytes)
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std r4,0(r10)
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std r4,8(r10)
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std r4,16(r10)
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std r4,24(r10)
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addi r10,10,32
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bdnz L(big_loop)
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b L(tail_bytes)
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/* Write remaining 1~31 bytes. */
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.align 4
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L(tail_bytes):
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beqlr cr6
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srdi r7,r11,4
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clrldi r8,r11,60
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mtocrf 0x01,r7
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.align 4
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bf 31,8f
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std r4,0(r10)
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std r4,8(r10)
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addi r10,r10,16
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.align 4
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8: mtocrf 0x1,r8
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bf 28,4f
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std r4,0(r10)
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addi r10,r10,8
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.align 4
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4: bf 29,2f
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stw 4,0(10)
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addi 10,10,4
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.align 4
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2: bf 30,1f
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sth 4,0(10)
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addi 10,10,2
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.align 4
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1: bflr 31
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stb 4,0(10)
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blr
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/* Size larger than 255 bytes with constant different than 0, use
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vector instruction to achieve best throughput. */
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L(huge_vector):
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/* Replicate set byte to quadword in VMX register. */
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MTVSRD_V1_R4
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xxpermdi 32,v0,v1,0
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vspltb v2,v0,15
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/* Main aligned write loop: 128 bytes at a time. */
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li r6,16
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li r7,32
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li r8,48
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mtocrf 0x02,r5
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srdi r12,r5,7
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cmpdi r12,0
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beq L(aligned_tail)
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mtctr r12
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b L(aligned_128loop)
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.align 4
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L(aligned_128loop):
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stvx v2,0,r10
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stvx v2,r10,r6
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stvx v2,r10,r7
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stvx v2,r10,r8
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addi r10,r10,64
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stvx v2,0,r10
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stvx v2,r10,r6
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stvx v2,r10,r7
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stvx v2,r10,r8
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addi r10,r10,64
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bdnz L(aligned_128loop)
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/* Write remaining 1~127 bytes. */
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L(aligned_tail):
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mtocrf 0x01,r5
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bf 25,32f
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stvx v2,0,r10
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stvx v2,r10,r6
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stvx v2,r10,r7
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stvx v2,r10,r8
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addi r10,r10,64
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32: bf 26,16f
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stvx v2,0,r10
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stvx v2,r10,r6
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addi r10,r10,32
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16: bf 27,8f
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stvx v2,0,r10
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addi r10,r10,16
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8: bf 28,4f
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std r4,0(r10)
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addi r10,r10,8
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/* Copies 4~7 bytes. */
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4: bf 29,L(tail2)
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stw r4,0(r10)
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bf 30,L(tail5)
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sth r4,4(r10)
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bflr 31
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stb r4,6(r10)
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/* Return original DST pointer. */
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blr
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/* Special case when value is 0 and we have a long length to deal
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with. Use dcbz to zero out a full cacheline of 128 bytes at a time.
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Before using dcbz though, we need to get the destination 128-byte
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aligned. */
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.align 4
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L(huge_dcbz):
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andi. r11,r10,127
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neg r0,r10
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beq L(huge_dcbz_aligned)
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clrldi r0,r0,57
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subf r5,r0,r5
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srdi r0,r0,3
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mtocrf 0x01,r0
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/* Write 1~128 bytes until DST is aligned to 128 bytes. */
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8: bf 28,4f
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std r4,0(r10)
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std r4,8(r10)
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std r4,16(r10)
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std r4,24(r10)
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std r4,32(r10)
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std r4,40(r10)
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std r4,48(r10)
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std r4,56(r10)
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addi r10,r10,64
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.align 4
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4: bf 29,2f
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std r4,0(r10)
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std r4,8(r10)
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std r4,16(r10)
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std r4,24(r10)
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addi r10,r10,32
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.align 4
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2: bf 30,1f
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std r4,0(r10)
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std r4,8(r10)
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addi r10,r10,16
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.align 4
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1: bf 31,L(huge_dcbz_aligned)
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std r4,0(r10)
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addi r10,r10,8
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L(huge_dcbz_aligned):
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/* Setup dcbz unroll offsets and count numbers. */
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srdi r8,r5,9
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clrldi r11,r5,55
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cmpldi cr6,r11,0
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li r9,128
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cmpdi r8,0
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beq L(huge_tail)
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li r7,256
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li r6,384
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mtctr r8
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.align 4
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L(huge_loop):
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/* Sets 512 bytes to zero in each iteration, the loop unrolling shows
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a throughput boost for large sizes (2048 bytes or higher). */
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dcbz 0,r10
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dcbz r9,r10
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dcbz r7,r10
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dcbz r6,r10
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addi r10,r10,512
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bdnz L(huge_loop)
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beqlr cr6
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L(huge_tail):
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srdi r6,r11,8
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srdi r7,r11,4
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clrldi r8,r11,4
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cmpldi cr6,r8,0
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mtocrf 0x01,r6
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beq cr6,L(tail)
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/* We have 1~511 bytes remaining. */
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.align 4
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32: bf 31,16f
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dcbz 0,r10
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dcbz r9,r10
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addi r10,r10,256
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.align 4
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16: mtocrf 0x01,r7
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bf 28,8f
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dcbz 0,r10
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addi r10,r10,128
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.align 4
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8: bf 29,4f
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std r4,0(r10)
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std r4,8(r10)
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std r4,16(r10)
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std r4,24(r10)
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std r4,32(r10)
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std r4,40(r10)
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std r4,48(r10)
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std r4,56(r10)
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addi r10,r10,64
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.align 4
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4: bf 30,2f
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std r4,0(r10)
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std r4,8(r10)
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std r4,16(r10)
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std r4,24(r10)
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addi r10,r10,32
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.align 4
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2: bf 31,L(tail)
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std r4,0(r10)
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std r4,8(r10)
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addi r10,r10,16
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.align 4
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/* Remaining 1~15 bytes. */
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L(tail):
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mtocrf 0x01,r8
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.align
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8: bf 28,4f
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std r4,0(r10)
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addi r10,r10,8
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.align 4
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4: bf 29,2f
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stw r4,0(r10)
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addi r10,r10,4
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.align 4
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2: bf 30,1f
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sth r4,0(r10)
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addi r10,r10,2
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.align 4
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1: bflr 31
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stb r4,0(r10)
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blr
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/* Handle short copies of 0~31 bytes. Best throughput is achieved
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by just unrolling all operations. */
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.align 4
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L(write_LT_32):
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cmpldi cr6,5,8
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mtocrf 0x01,r5
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ble cr6,L(write_LE_8)
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/* At least 9 bytes to go. */
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neg r8,r4
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andi. r0,r8,3
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cmpldi cr1,r5,16
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beq L(write_LT_32_aligned)
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/* Force 4-byte alignment for SRC. */
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mtocrf 0x01,r0
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subf r5,r0,r5
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2: bf 30,1f
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sth r4,0(r10)
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addi r10,r10,2
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1: bf 31,L(end_4bytes_alignment)
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stb r4,0(r10)
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addi r10,r10,1
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.align 4
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L(end_4bytes_alignment):
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cmpldi cr1,r5,16
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mtocrf 0x01,r5
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L(write_LT_32_aligned):
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blt cr1,8f
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stw r4,0(r10)
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stw r4,4(r10)
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stw r4,8(r10)
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stw r4,12(r10)
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addi r10,r10,16
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8: bf 28,L(tail4)
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stw r4,0(r10)
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stw r4,4(r10)
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addi r10,r10,8
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.align 4
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/* Copies 4~7 bytes. */
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L(tail4):
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bf 29,L(tail2)
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stw r4,0(r10)
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bf 30,L(tail5)
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sth r4,4(r10)
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bflr 31
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stb r4,6(r10)
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blr
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.align 4
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/* Copies 2~3 bytes. */
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L(tail2):
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bf 30,1f
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sth r4,0(r10)
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bflr 31
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stb r4,2(r10)
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blr
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.align 4
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L(tail5):
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bflr 31
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stb r4,4(r10)
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blr
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.align 4
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1: bflr 31
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stb r4,0(r10)
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blr
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/* Handles copies of 0~8 bytes. */
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.align 4
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L(write_LE_8):
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bne cr6,L(tail4)
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stw r4,0(r10)
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stw r4,4(r10)
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blr
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END_GEN_TB (memset,TB_TOCLESS)
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libc_hidden_builtin_def (memset)
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/* Copied from bzero.S to prevent the linker from inserting a stub
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between bzero and memset. */
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ENTRY (__bzero)
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CALL_MCOUNT 3
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mr r5,r4
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li r4,0
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b L(_memset)
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END (__bzero)
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#ifndef __bzero
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weak_alias (__bzero, bzero)
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#endif
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