mirror of
https://sourceware.org/git/glibc.git
synced 2025-08-21 22:22:50 +03:00
5 lines
209 B
C
5 lines
209 B
C
/* 4 instruction cycles not accessing cache and TLB are needed after
|
|
trapa instruction to avoid an SH-4 silicon bug. */
|
|
#define NEED_SYSCALL_INST_PAD
|
|
#include <sysdeps/unix/sysv/linux/sh/lowlevellock.h>
|