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sed -ri '
s,(http|ftp)(://(.*\.)?(gnu|fsf|sourceware)\.org($|[^.]|\.[^a-z])),https\2,g
s,(http|ftp)(://(.*\.)?)sources\.redhat\.com($|[^.]|\.[^a-z]),https\2sourceware.org\4,g
' \
$(find $(git ls-files) -prune -type f \
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! -path COPYING ! -path COPYING.LIB \
! -path manual/fdl-1.3.texi ! -path manual/lgpl-2.1.texi \
! -path manual/texinfo.tex ! -path scripts/config.guess \
! -path scripts/config.sub ! -path scripts/install-sh \
! -path scripts/mkinstalldirs ! -path scripts/move-if-change \
! -path INSTALL ! -path locale/programs/charmap-kw.h \
! -path po/libc.pot ! -path sysdeps/gnu/errlist.c \
! '(' -name configure \
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! '(' -name preconfigure \
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-print)
and then by running 'make dist-prepare' to regenerate files built
from the altered files, and then executing the following to cleanup:
chmod a+x sysdeps/unix/sysv/linux/riscv/configure
# Omit irrelevant whitespace and comment-only changes,
# perhaps from a slightly-different Autoconf version.
git checkout -f \
sysdeps/csky/configure \
sysdeps/hppa/configure \
sysdeps/riscv/configure \
sysdeps/unix/sysv/linux/csky/configure
# Omit changes that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/powerpc/powerpc64/ppc-mcount.S: trailing lines
git checkout -f \
sysdeps/powerpc/powerpc64/ppc-mcount.S \
sysdeps/unix/sysv/linux/s390/s390-64/syscall.S
# Omit change that caused a pre-commit check to fail like this:
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git checkout -f sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S
127 lines
4.4 KiB
C
127 lines
4.4 KiB
C
/* Atomic operations. PowerPC32 version.
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Copyright (C) 2003-2019 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* POWER6 adds a "Mutex Hint" to the Load and Reserve instruction.
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This is a hint to the hardware to expect additional updates adjacent
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to the lock word or not. If we are acquiring a Mutex, the hint
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should be true. Otherwise we releasing a Mutex or doing a simple
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atomic operation. In that case we don't expect additional updates
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adjacent to the lock word after the Store Conditional and the hint
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should be false. */
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#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
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# define MUTEX_HINT_ACQ ",1"
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# define MUTEX_HINT_REL ",0"
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#else
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# define MUTEX_HINT_ACQ
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# define MUTEX_HINT_REL
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#endif
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#define __HAVE_64B_ATOMICS 0
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#define USE_ATOMIC_COMPILER_BUILTINS 0
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#define ATOMIC_EXCHANGE_USES_CAS 1
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/*
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* The 32-bit exchange_bool is different on powerpc64 because the subf
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* does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
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* (a load word and zero (high 32) form). So powerpc64 has a slightly
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* different version in sysdeps/powerpc/powerpc64/atomic-machine.h.
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*/
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#define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
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({ \
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unsigned int __tmp; \
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__asm __volatile ( \
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"1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
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" subf. %0,%2,%0\n" \
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" bne 2f\n" \
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" stwcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "b" (mem), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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/* Powerpc32 processors don't implement the 64-bit (doubleword) forms of
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load and reserve (ldarx) and store conditional (stdcx.) instructions.
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So for powerpc32 we stub out the 64-bit forms. */
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#define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
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(abort (), 0)
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#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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(abort (), (__typeof (*mem)) 0)
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#define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \
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(abort (), (__typeof (*mem)) 0)
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#define __arch_atomic_exchange_64_acq(mem, value) \
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({ abort (); (*mem) = (value); })
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#define __arch_atomic_exchange_64_rel(mem, value) \
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({ abort (); (*mem) = (value); })
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#define __arch_atomic_exchange_and_add_64(mem, value) \
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({ abort (); (*mem) = (value); })
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#define __arch_atomic_exchange_and_add_64_acq(mem, value) \
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({ abort (); (*mem) = (value); })
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#define __arch_atomic_exchange_and_add_64_rel(mem, value) \
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({ abort (); (*mem) = (value); })
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#define __arch_atomic_increment_val_64(mem) \
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({ abort (); (*mem)++; })
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#define __arch_atomic_decrement_val_64(mem) \
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({ abort (); (*mem)--; })
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#define __arch_atomic_decrement_if_positive_64(mem) \
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({ abort (); (*mem)--; })
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#ifdef _ARCH_PWR4
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/*
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* Newer powerpc64 processors support the new "light weight" sync (lwsync)
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* So if the build is using -mcpu=[power4,power5,power5+,970] we can
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* safely use lwsync.
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*/
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# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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/*
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* "light weight" sync can also be used for the release barrier.
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*/
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# ifndef UP
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# define __ARCH_REL_INSTR "lwsync"
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# endif
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# define atomic_write_barrier() __asm ("lwsync" ::: "memory")
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#else
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/*
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* Older powerpc32 processors don't support the new "light weight"
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* sync (lwsync). So the only safe option is to use normal sync
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* for all powerpc32 applications.
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*/
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# define atomic_read_barrier() __asm ("sync" ::: "memory")
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# define atomic_write_barrier() __asm ("sync" ::: "memory")
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#endif
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/*
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* Include the rest of the atomic ops macros which are common to both
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* powerpc32 and powerpc64.
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*/
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#include_next <atomic-machine.h>
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