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25f1e16ef0
CET is only support for x86_64, this patch reverts: -faaee1f07ex86: Support shadow stack pointer in setjmp/longjmp. -be9ccd27c0i386: Add _CET_ENDBR to indirect jump targets in add_n.S/sub_n.S -c02695d776x86/CET: Update vfork to prevent child return -5d844e1b72i386: Enable CET support in ucontext functions -124bcde683x86: Add _CET_ENDBR to functions in crti.S -562837c002x86: Add _CET_ENDBR to functions in dl-tlsdesc.S -f753fa7deax86: Support IBT and SHSTK in Intel CET [BZ #21598] -825b58f3fbi386-mcount.S: Add _CET_ENDBR to _mcount and __fentry__ -7e119cd582i386: Use _CET_NOTRACK in i686/memcmp.S -177824e232i386: Use _CET_NOTRACK in memcmp-sse4.S -0a899af097i386: Use _CET_NOTRACK in memcpy-ssse3-rep.S -7fb613361ci386: Use _CET_NOTRACK in memcpy-ssse3.S -77a8ae0948i386: Use _CET_NOTRACK in memset-sse2-rep.S -00e7b76a8fi386: Use _CET_NOTRACK in memset-sse2.S -90d15dc577i386: Use _CET_NOTRACK in strcat-sse2.S -f1574581c7i386: Use _CET_NOTRACK in strcpy-sse2.S -4031d7484ai386/sub_n.S: Add a missing _CET_ENDBR to indirect jump - target - Checked on i686-linux-gnu.
77 lines
2.3 KiB
ArmAsm
77 lines
2.3 KiB
ArmAsm
/* Save current context.
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Copyright (C) 2001-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include "ucontext_i.h"
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ENTRY(__getcontext)
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/* Load address of the context data structure. */
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movl 4(%esp), %eax
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/* Save the preserved register values and the return address. */
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movl %edi, oEDI(%eax)
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movl %esi, oESI(%eax)
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movl %ebp, oEBP(%eax)
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movl (%esp), %ecx
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movl %ecx, oEIP(%eax)
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leal 4(%esp), %ecx /* Exclude the return address. */
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movl %ecx, oESP(%eax)
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movl %ebx, oEBX(%eax)
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/* Save the FS segment register. We don't touch the GS register
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since it is used for threads. */
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xorl %edx, %edx
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movw %fs, %dx
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movl %edx, oFS(%eax)
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/* We have separate floating-point register content memory on the
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stack. We use the __fpregs_mem block in the context. Set the
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links up correctly. */
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leal oFPREGSMEM(%eax), %ecx
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movl %ecx, oFPREGS(%eax)
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/* Save the floating-point context. */
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fnstenv (%ecx)
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/* And load it right back since the processor changes the mask.
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Intel thought this opcode to be used in interrupt handlers which
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would block all exceptions. */
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fldenv (%ecx)
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/* Save the current signal mask. */
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pushl %ebx
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cfi_adjust_cfa_offset (4)
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cfi_rel_offset (ebx, 0)
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leal oSIGMASK(%eax), %edx
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xorl %ecx, %ecx
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movl $SIG_BLOCK, %ebx
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movl $__NR_sigprocmask, %eax
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ENTER_KERNEL
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popl %ebx
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cfi_adjust_cfa_offset (-4)
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cfi_restore (ebx)
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cmpl $-4095, %eax /* Check %eax for error. */
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jae SYSCALL_ERROR_LABEL /* Jump to error handler if error. */
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/* All done, return 0 for success. */
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xorl %eax, %eax
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ret
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PSEUDO_END(__getcontext)
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weak_alias (__getcontext, getcontext)
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