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90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/* FPU control word bits. OpenRISC version.
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Copyright (C) 2024-2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _FPU_CONTROL_H
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#define _FPU_CONTROL_H
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#ifndef __or1k_hard_float__
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# define _FPU_RESERVED 0xffffffff
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# define _FPU_DEFAULT 0x00000000
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# define _FPU_GETCW(cw) (cw) = 0
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# define _FPU_SETCW(cw) (void) (cw)
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#else /* __or1k_hard_float__ */
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/* Layout of FPCSR:
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The bits of the FPCSR are defined as follows, this should help
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explain how the masks below have come to be.
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+-----------+----------------------------+-----+----+
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| 32 - 12 | 11 10 9 8 7 6 5 4 3 | 2-1 | 0 |
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+-----------+----------------------------+-----+----+
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| Reserved | DZ IN IV IX Z QN SN UN OV | RM | EE |
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+-----------+----------------------------+-----+----+
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Exception flags:
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DZ - divide by zero flag.
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IN - infinite flag.
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IV - invalid flag.
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IX - inexact flag.
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Z - zero flag.
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QN - qnan flag.
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SN - snan flag.
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UN - underflow flag.
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OV - overflow flag.
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Rounding modes:
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The FPCSR bits 2-1 labeled above as RM specify the rounding mode.
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00 - round to nearest
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01 - round to zero
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10 - round to positive infinity
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11 - round to negative infinity
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Enabling exceptions:
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EE - set to enable FPU exceptions.
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*/
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# define _FPU_RESERVED 0xfffff000
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/* Default: rounding to nearest with exceptions disabled. */
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# define _FPU_DEFAULT 0
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/* IEEE: Same as above with exceptions enabled. */
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# define _FPU_IEEE (_FPU_DEFAULT | 1)
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# define _FPU_FPCSR_RM_MASK (0x3 << 1)
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/* Macros for accessing the hardware control word. */
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# define _FPU_GETCW(cw) __asm__ volatile ("l.mfspr %0,r0,20" : "=r" (cw))
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# define _FPU_SETCW(cw) __asm__ volatile ("l.mtspr r0,%0,20" : : "r" (cw))
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#endif /* __or1k_hard_float__ */
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/* Type of the control word. */
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typedef unsigned int fpu_control_t;
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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#endif /* fpu_control.h */
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