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I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 6694 files FOO. I then removed trailing white space from benchtests/bench-pthread-locks.c and iconvdata/tst-iconv-big5-hkscs-to-2ucs4.c, to work around this diagnostic from Savannah: remote: *** pre-commit check failed ... remote: *** error: lines with trailing whitespace found remote: error: hook declined to update refs/heads/master
168 lines
3.4 KiB
C
168 lines
3.4 KiB
C
/* Copyright (C) 1999-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/*
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* Powerpc Feature masks for the Aux Vector Hardware Capabilities (AT_HWCAP).
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* This entry is copied to _dl_hwcap or rtld_global._dl_hwcap during startup.
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*/
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#define _SYSDEPS_SYSDEP_H 1
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#include <bits/hwcap.h>
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#define PPC_FEATURE_970 (PPC_FEATURE_POWER4 + PPC_FEATURE_HAS_ALTIVEC)
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#ifdef __ASSEMBLER__
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/* Symbolic names for the registers. The only portable way to write asm
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code is to use number but this produces really unreadable code.
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Therefore these symbolic names. */
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/* Integer registers. */
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#define r0 0
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#define r1 1
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#define r2 2
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#define r3 3
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#define r4 4
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#define r5 5
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#define r6 6
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#define r7 7
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#define r8 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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/* Floating-point registers. */
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#define fp0 0
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#define fp1 1
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#define fp2 2
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#define fp3 3
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#define fp4 4
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#define fp5 5
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#define fp6 6
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#define fp7 7
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#define fp8 8
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#define fp9 9
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#define fp10 10
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#define fp11 11
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#define fp12 12
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#define fp13 13
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#define fp14 14
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#define fp15 15
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#define fp16 16
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#define fp17 17
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#define fp18 18
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#define fp19 19
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#define fp20 20
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#define fp21 21
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#define fp22 22
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#define fp23 23
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#define fp24 24
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#define fp25 25
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#define fp26 26
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#define fp27 27
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#define fp28 28
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#define fp29 29
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#define fp30 30
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#define fp31 31
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/* Condition code registers. */
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#define cr0 0
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#define cr1 1
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#define cr2 2
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#define cr3 3
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#define cr4 4
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#define cr5 5
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#define cr6 6
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#define cr7 7
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/* Vector registers. */
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#define v0 0
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#define v1 1
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#define v2 2
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#define v3 3
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#define v4 4
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#define v5 5
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#define v6 6
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#define v7 7
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#define v8 8
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#define v9 9
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#define v10 10
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#define v11 11
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#define v12 12
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#define v13 13
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#define v14 14
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#define v15 15
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#define v16 16
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#define v17 17
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#define v18 18
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#define v19 19
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#define v20 20
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#define v21 21
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#define v22 22
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#define v23 23
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#define v24 24
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#define v25 25
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#define v26 26
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#define v27 27
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#define v28 28
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#define v29 29
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#define v30 30
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#define v31 31
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#define VRSAVE 256
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/* The 32-bit words of a 64-bit dword are at these offsets in memory. */
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#if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN
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# define LOWORD 0
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# define HIWORD 4
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#else
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# define LOWORD 4
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# define HIWORD 0
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#endif
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/* The high 16-bit word of a 64-bit dword is at this offset in memory. */
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#if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN
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# define HISHORT 6
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#else
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# define HISHORT 0
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#endif
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/* This seems to always be the case on PPC. */
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#define ALIGNARG(log2) log2
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#define ASM_SIZE_DIRECTIVE(name) .size name,.-name
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#endif /* __ASSEMBLER__ */
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