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	I've moved the MIPS port from ports to the main sysdeps hierarchy. Beyond the README update, the move of the files was simply git mv ports/sysdeps/mips sysdeps/mips git mv ports/sysdeps/unix/mips sysdeps/unix/mips git mv ports/sysdeps/unix/sysv/linux/mips sysdeps/unix/sysv/linux/mips and in addition to the ChangeLog entries here, I put a note at the top of ports/ChangeLog.mips similar to those in other files. Tested that disassembly of installed shared libraries for mips is the same before and after this patch (except for ld.so where paths in assertions are involved, as for arm). * sysdeps/mips: Move directory from ports/sysdeps/mips. * sysdeps/unix/mips: Move directory from ports/sysdeps/unix/mips. * sysdeps/unix/sysv/linux/mips: Move directory from ports/sysdeps/unix/sysv/linux/mips. * README: Update listing for mips-*-linux-gnu and mips64-*-linux-gnu. * sysdeps/mips: Move directory to ../sysdeps/mips. * sysdeps/unix/mips: Move directory to ../sysdeps/unix/mips. * sysdeps/unix/sysv/linux/mips: Move directory to ../sysdeps/unix/sysv/linux/mips.
		
			
				
	
	
		
			159 lines
		
	
	
		
			3.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			159 lines
		
	
	
		
			3.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* Copyright (C) 1998-2014 Free Software Foundation, Inc.
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|    This file is part of the GNU C Library.
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| 
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|    The GNU C Library is free software; you can redistribute it and/or
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|    modify it under the terms of the GNU Lesser General Public
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|    License as published by the Free Software Foundation; either
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|    version 2.1 of the License, or (at your option) any later version.
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| 
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|    The GNU C Library is distributed in the hope that it will be useful,
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|    but WITHOUT ANY WARRANTY; without even the implied warranty of
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|    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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|    Lesser General Public License for more details.
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| 
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|    You should have received a copy of the GNU Lesser General Public
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|    License along with the GNU C Library.  If not, see
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|    <http://www.gnu.org/licenses/>.  */
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| 
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| /* System V/mips ABI compliant context switching support.  */
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| 
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| #ifndef _SYS_UCONTEXT_H
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| #define _SYS_UCONTEXT_H	1
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| 
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| #include <features.h>
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| #include <sgidefs.h>
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| #include <signal.h>
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| 
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| /* Type for general register.  */
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| #if _MIPS_SIM == _ABIO32
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| typedef __uint32_t greg_t;
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| #else
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| typedef __uint64_t greg_t;
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| #endif
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| 
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| /* Number of general registers.  */
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| #define NGREG	36
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| 
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| /* Container for all general registers.  */
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| typedef greg_t gregset_t[NGREG];
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| 
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| /* Number of each register is the `gregset_t' array.  */
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| enum
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| {
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|   CTX_R0 = 0,
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| #define CTX_R0	CTX_R0
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|   CTX_AT = 1,
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| #define CTX_AT	CTX_AT
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|   CTX_V0 = 2,
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| #define CTX_V0	CTX_V0
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|   CTX_V1 = 3,
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| #define CTX_V1	CTX_V1
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|   CTX_A0 = 4,
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| #define CTX_A0	CTX_A0
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|   CTX_A1 = 5,
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| #define CTX_A1	CTX_A1
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|   CTX_A2 = 6,
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| #define CTX_A2	CTX_A2
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|   CTX_A3 = 7,
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| #define CTX_A3	CTX_A3
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|   CTX_T0 = 8,
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| #define CTX_T0	CTX_T0
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|   CTX_T1 = 9,
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| #define CTX_T1	CTX_T1
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|   CTX_T2 = 10,
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| #define CTX_T2	CTX_T2
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|   CTX_T3 = 11,
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| #define CTX_T3	CTX_T3
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|   CTX_T4 = 12,
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| #define CTX_T4	CTX_T4
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|   CTX_T5 = 13,
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| #define CTX_T5	CTX_T5
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|   CTX_T6 = 14,
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| #define CTX_T6	CTX_T6
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|   CTX_T7 = 15,
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| #define CTX_T7	CTX_T7
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|   CTX_S0 = 16,
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| #define CTX_S0	CTX_S0
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|   CTX_S1 = 17,
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| #define CTX_S1	CTX_S1
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|   CTX_S2 = 18,
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| #define CTX_S2	CTX_S2
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|   CTX_S3 = 19,
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| #define CTX_S3	CTX_S3
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|   CTX_S4 = 20,
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| #define CTX_S4	CTX_S4
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|   CTX_S5 = 21,
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| #define CTX_S5	CTX_S5
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|   CTX_S6 = 22,
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| #define CTX_S6	CTX_S6
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|   CTX_S7 = 23,
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| #define CTX_S7	CTX_S7
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|   CTX_T8 = 24,
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| #define CTX_T8	CTX_T8
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|   CTX_T9 = 25,
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| #define CTX_T9	CTX_T9
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|   CTX_K0 = 26,
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| #define CTX_K0	CTX_K0
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|   CTX_K1 = 27,
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| #define CTX_K1	CTX_K1
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|   CTX_GP = 28,
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| #define CTX_GP	CTX_GP
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|   CTX_SP = 29,
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| #define CTX_SP	CTX_SP
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|   CTX_S8 = 30,
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| #define CTX_S8	CTX_S8
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|   CTX_RA = 31,
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| #define CTX_RA	CTX_RA
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|   CTX_MDLO = 32,
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| #define CTX_MDLO	CTX_MDLO
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|   CTX_MDHI = 33,
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| #define CTX_MDHI	CTX_MDHI
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|   CTX_CAUSE = 34,
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| #define CTX_CAUSE	CTX_CAUSE
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|   CTX_EPC = 35,
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| #define CTX_EPC	CTX_EPC
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| };
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| 
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| /* Structure to describe FPU registers.  */
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| typedef struct fpregset
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| {
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|   union
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|   {
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| #if _MIPS_SIM == _ABIO32
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|     double fp_dregs[16];
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|     float fp_fregs[32];
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|     unsigned int fp_regs[32];
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| #else
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|     double fp_dregs[32];
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|     /* float fp_fregs[32]; */
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|     __uint64_t fp_regs[32];
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| #endif
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|   } fp_r;
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|   unsigned int fp_csr;
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|   unsigned int fp_pad;
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| } fpregset_t;
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| 
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| /* Context to describe whole processor state.  */
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| typedef struct
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| {
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|   gregset_t gpregs;
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|   fpregset_t fpregs;
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| } mcontext_t;
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| 
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| /* Userlevel context.  */
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| typedef struct ucontext
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| {
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| #if _MIPS_SIM == _ABIO32
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|   unsigned long int uc_flags;
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| #else
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|   __uint64_t uc_flags;
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| #endif
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|   struct ucontext *uc_link;
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|   __sigset_t uc_sigmask;
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|   stack_t uc_stack;
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|   mcontext_t uc_mcontext;
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|   int uc_filler[48];
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| } ucontext_t;
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| 
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| #endif /* sys/ucontext.h */
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