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6c575d835e
clang issues: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths] while tryng to use 32 bit variables with 'mrs' to get/set the fpsr, dczid_el0, and ctr.
56 lines
1.9 KiB
C
56 lines
1.9 KiB
C
/* Copyright (C) 2017-2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <assert.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <unistd.h>
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static long int linux_sysconf (int name);
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/* Get the value of the system variable NAME. */
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long int
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__sysconf (int name)
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{
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uint64_t ctr;
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/* Unfortunately, the registers that contain the actual cache info
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(CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux
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kernel (though they need not have been). However, CTR_EL0 contains
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the *minimum* linesize in the entire cache hierarchy, and is
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accessible to userland, for use in __aarch64_sync_cache_range,
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and it is a reasonable assumption that the L1 cache will have that
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minimum line size. */
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switch (name)
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{
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case _SC_LEVEL1_ICACHE_LINESIZE:
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asm("mrs\t%0, ctr_el0" : "=r"(ctr));
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return 4 << (ctr & 0xf);
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case _SC_LEVEL1_DCACHE_LINESIZE:
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asm("mrs\t%0, ctr_el0" : "=r"(ctr));
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return 4 << ((ctr >> 16) & 0xf);
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}
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return linux_sysconf (name);
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}
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/* Now the generic Linux version. */
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#undef __sysconf
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#define __sysconf static linux_sysconf
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#include <sysdeps/unix/sysv/linux/sysconf.c>
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