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* sysdeps/mips/atomicity.h: Remove unused file. * sysdeps/mips/dl-machine.h (elf_machine_rel): Add TLS relocations. * sysdeps/mips/dl-tls.h: New file. * sysdeps/mips/libc-tls.c: New file. * sysdeps/mips/tls-macros.h: New file. * sysdeps/mips/bits/atomic.h: New file. * sysdeps/mips/bits/setjmp.h: Protect against multiple inclusion. * sysdeps/mips/elf/configure.in: New file. * sysdeps/mips/elf/configure: Generated. * sysdeps/mips/sys/asm.h: New file. * sysdeps/unix/sysv/linux/mips/vfork.S: New file. * sysdeps/unix/sysv/linux/mips/clone.S: Add NPTL and five-argument clone support. * sysdeps/unix/sysv/linux/mips/mips32/sysdep.h (INTERNAL_SYSCALL_NCS): New. (INTERNAL_SYSCALL): Update for non-constant support. (internal_syscall0): Likewise. (internal_syscall1): Likewise. (internal_syscall2): Likewise. (internal_syscall3): Likewise. (internal_syscall4): Likewise. (internal_syscall5): Likewise. (internal_syscall6): Likewise. (internal_syscall7): Likewise. * sysdeps/unix/sysv/linux/mips/bits/siginfo.h (SIGEV_THREAD): Update to match the kernel. (SIGEV_CALLBACK): Likewise. (SIGEV_THREAD_ID): Likewise. 2005-03-28 Daniel Jacobowitz <dan@codesourcery.com>
304 lines
10 KiB
C
304 lines
10 KiB
C
/* Low-level functions for atomic operations. Mips version.
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Copyright (C) 2005 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#ifndef _MIPS_BITS_ATOMIC_H
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#define _MIPS_BITS_ATOMIC_H 1
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#include <inttypes.h>
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#include <sgidefs.h>
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typedef int32_t atomic32_t;
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typedef uint32_t uatomic32_t;
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typedef int_fast32_t atomic_fast32_t;
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typedef uint_fast32_t uatomic_fast32_t;
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typedef int64_t atomic64_t;
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typedef uint64_t uatomic64_t;
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typedef int_fast64_t atomic_fast64_t;
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typedef uint_fast64_t uatomic_fast64_t;
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typedef intptr_t atomicptr_t;
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typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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#if _MIPS_SIM == _ABIO32
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#define MIPS_PUSH_MIPS2 ".set mips2\n\t"
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#else
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#define MIPS_PUSH_MIPS2
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#endif
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/* See the comments in <sys/asm.h> about the use of the sync instruction. */
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#ifndef MIPS_SYNC
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# define MIPS_SYNC sync
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#endif
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#define MIPS_SYNC_STR_2(X) #X
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#define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X)
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#define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC)
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/* Compare and exchange. For all of the "xxx" routines, we expect a
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"__prev" and a "__cmp" variable to be provided by the enclosing scope,
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in which values are returned. */
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#define __arch_compare_and_exchange_xxx_8_int(mem, newval, oldval, rel, acq) \
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(abort (), __prev = __cmp = 0)
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#define __arch_compare_and_exchange_xxx_16_int(mem, newval, oldval, rel, acq) \
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(abort (), __prev = __cmp = 0)
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#define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, acq) \
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__asm__ __volatile__ ( \
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".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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rel "\n" \
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"1:\t" \
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"ll %0,%4\n\t" \
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"move %1,$0\n\t" \
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"bne %0,%2,2f\n\t" \
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"move %1,%3\n\t" \
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"sc %1,%4\n\t" \
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"beqz %1,1b\n" \
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acq "\n\t" \
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".set pop\n" \
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"2:\n\t" \
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: "=&r" (__prev), "=&r" (__cmp) \
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: "r" (oldval), "r" (newval), "m" (*mem) \
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: "memory")
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#if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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#define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
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(abort (), __prev = __cmp = 0)
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#else
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#define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
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__asm__ __volatile__ ("\n" \
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".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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rel "\n" \
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"1:\t" \
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"lld %0,%4\n\t" \
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"move %1,$0\n\t" \
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"bne %0,%2,2f\n\t" \
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"move %1,%3\n\t" \
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"scd %1,%4\n\t" \
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"beqz %1,1b\n" \
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acq "\n\t" \
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".set pop\n" \
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"2:\n\t" \
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: "=&r" (__prev), "=&r" (__cmp) \
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: "r" (oldval), "r" (newval), "m" (*mem) \
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: "memory")
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#endif
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/* For all "bool" routines, we return FALSE if exchange succesful. */
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#define __arch_compare_and_exchange_bool_8_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \
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!__cmp; })
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#define __arch_compare_and_exchange_bool_16_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \
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!__cmp; })
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#define __arch_compare_and_exchange_bool_32_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \
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!__cmp; })
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#define __arch_compare_and_exchange_bool_64_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \
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!__cmp; })
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/* For all "val" routines, return the old value whether exchange
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successful or not. */
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#define __arch_compare_and_exchange_val_8_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \
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(typeof (*mem))__prev; })
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#define __arch_compare_and_exchange_val_16_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \
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(typeof (*mem))__prev; })
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#define __arch_compare_and_exchange_val_32_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \
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(typeof (*mem))__prev; })
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#define __arch_compare_and_exchange_val_64_int(mem, new, old, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \
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(typeof (*mem))__prev; })
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/* Compare and exchange with "acquire" semantics, ie barrier after. */
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#define atomic_compare_and_exchange_bool_acq(mem, new, old) \
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__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
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mem, new, old, "", MIPS_SYNC_STR)
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#define atomic_compare_and_exchange_val_acq(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, "", MIPS_SYNC_STR)
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/* Compare and exchange with "release" semantics, ie barrier before. */
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#define atomic_compare_and_exchange_bool_rel(mem, new, old) \
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__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
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mem, new, old, MIPS_SYNC_STR, "")
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#define atomic_compare_and_exchange_val_rel(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, MIPS_SYNC_STR, "")
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/* Atomic exchange (without compare). */
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#define __arch_exchange_xxx_8_int(mem, newval, rel, acq) \
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(abort (), 0)
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#define __arch_exchange_xxx_16_int(mem, newval, rel, acq) \
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(abort (), 0)
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#define __arch_exchange_xxx_32_int(mem, newval, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__asm__ __volatile__ ("\n" \
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".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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rel "\n" \
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"1:\t" \
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"ll %0,%3\n\t" \
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"move %1,%2\n\t" \
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"sc %1,%3\n\t" \
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"beqz %1,1b\n" \
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acq "\n\t" \
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".set pop\n" \
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"2:\n\t" \
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: "=&r" (__prev), "=&r" (__cmp) \
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: "r" (newval), "m" (*mem) \
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: "memory"); \
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__prev; })
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#if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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#define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
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(abort (), 0)
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#else
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#define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__asm__ __volatile__ ("\n" \
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".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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rel "\n" \
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"1:\n" \
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"lld %0,%3\n\t" \
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"move %1,%2\n\t" \
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"scd %1,%3\n\t" \
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"beqz %1,1b\n" \
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acq "\n\t" \
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".set pop\n" \
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"2:\n\t" \
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: "=&r" (__prev), "=&r" (__cmp) \
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: "r" (newval), "m" (*mem) \
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: "memory"); \
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__prev; })
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#endif
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#define atomic_exchange_acq(mem, value) \
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__atomic_val_bysize (__arch_exchange_xxx, int, mem, value, "", MIPS_SYNC_STR)
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#define atomic_exchange_rel(mem, value) \
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__atomic_val_bysize (__arch_exchange_xxx, int, mem, value, MIPS_SYNC_STR, "")
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/* Atomically add value and return the previous (unincremented) value. */
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#define __arch_exchange_and_add_8_int(mem, newval, rel, acq) \
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(abort (), (typeof(*mem)) 0)
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#define __arch_exchange_and_add_16_int(mem, newval, rel, acq) \
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(abort (), (typeof(*mem)) 0)
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#define __arch_exchange_and_add_32_int(mem, value, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__asm__ __volatile__ ("\n" \
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".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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rel "\n" \
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"1:\t" \
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"ll %0,%3\n\t" \
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"addu %1,%0,%2\n\t" \
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"sc %1,%3\n\t" \
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"beqz %1,1b\n" \
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acq "\n\t" \
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".set pop\n" \
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"2:\n\t" \
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: "=&r" (__prev), "=&r" (__cmp) \
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: "r" (value), "m" (*mem) \
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: "memory"); \
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__prev; })
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#if _MIPS_SIM == _ABIO32
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/* We can't do an atomic 64-bit operation in O32. */
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#define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
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(abort (), (typeof(*mem)) 0)
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#else
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#define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
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({ typeof (*mem) __prev; int __cmp; \
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__asm__ __volatile__ ( \
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".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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rel "\n" \
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"1:\t" \
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"lld %0,%3\n\t" \
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"daddu %1,%0,%2\n\t" \
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"scd %1,%3\n\t" \
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"beqz %1,1b\n" \
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acq "\n\t" \
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".set pop\n" \
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"2:\n\t" \
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: "=&r" (__prev), "=&r" (__cmp) \
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: "r" (value), "m" (*mem) \
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: "memory"); \
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__prev; })
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#endif
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/* ??? Barrier semantics for atomic_exchange_and_add appear to be
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undefined. Use full barrier for now, as that's safe. */
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#define atomic_exchange_and_add(mem, value) \
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__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
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MIPS_SYNC_STR, MIPS_SYNC_STR)
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/* TODO: More atomic operations could be implemented efficiently; only the
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basic requirements are done. */
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#define atomic_full_barrier() \
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__asm__ __volatile__ (".set push\n\t" \
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MIPS_PUSH_MIPS2 \
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MIPS_SYNC_STR "\n\t" \
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".set pop" : : : "memory")
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#endif /* bits/atomic.h */
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