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2001-07-06 Paul Eggert <eggert@twinsun.com> * manual/argp.texi: Remove ignored LGPL copyright notice; it's not appropriate for documentation anyway. * manual/libc-texinfo.sh: "Library General Public License" -> "Lesser General Public License". 2001-07-06 Andreas Jaeger <aj@suse.de> * All files under GPL/LGPL version 2: Place under LGPL version 2.1.
103 lines
3.8 KiB
C
103 lines
3.8 KiB
C
/* FPU control word definitions. ARM version.
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Copyright (C) 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#ifndef _FPU_CONTROL_H
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#define _FPU_CONTROL_H
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/* We have a slight terminology confusion here. On the ARM, the register
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* we're interested in is actually the FPU status word - the FPU control
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* word is something different (which is implementation-defined and only
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* accessible from supervisor mode.)
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*
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* The FPSR looks like this:
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*
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* 31-24 23-16 15-8 7-0
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* | system ID | trap enable | system control | exception flags |
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*
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* We ignore the system ID bits; for interest's sake they are:
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*
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* 0000 "old" FPE
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* 1000 FPPC hardware
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* 0001 FPE 400
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* 1001 FPA hardware
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*
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* The trap enable and exception flags are both structured like this:
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*
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* 7 - 5 4 3 2 1 0
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* | reserved | INX | UFL | OFL | DVZ | IVO |
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*
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* where a `1' bit in the enable byte means that the trap can occur, and
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* a `1' bit in the flags byte means the exception has occurred.
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*
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* The exceptions are:
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*
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* IVO - invalid operation
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* DVZ - divide by zero
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* OFL - overflow
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* UFL - underflow
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* INX - inexact (do not use; implementations differ)
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*
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* The system control byte looks like this:
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*
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* 7-5 4 3 2 1 0
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* | reserved | AC | EP | SO | NE | ND |
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*
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* where the bits mean
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*
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* ND - no denormalised numbers (force them all to zero)
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* NE - enable NaN exceptions
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* SO - synchronous operation
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* EP - use expanded packed-decimal format
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* AC - use alternate definition for C flag on compare operations
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*/
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/* masking of interrupts */
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#define _FPU_MASK_IM 0x00010000 /* invalid operation */
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#define _FPU_MASK_ZM 0x00020000 /* divide by zero */
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#define _FPU_MASK_OM 0x00040000 /* overflow */
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#define _FPU_MASK_UM 0x00080000 /* underflow */
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#define _FPU_MASK_PM 0x00100000 /* inexact */
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#define _FPU_MASK_DM 0x00000000 /* denormalized operation */
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/* The system id bytes cannot be changed.
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Only the bottom 5 bits in the trap enable byte can be changed.
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Only the bottom 5 bits in the system control byte can be changed.
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Only the bottom 5 bits in the exception flags are used.
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The exception flags are set by the fpu, but can be zeroed by the user. */
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#define _FPU_RESERVED 0xffe0e0e0 /* These bits are reserved. */
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/* The fdlibm code requires strict IEEE double precision arithmetic,
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no interrupts for exceptions, rounding to nearest. Changing the
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rounding mode will break long double I/O. Turn on the AC bit,
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the compiler generates code that assumes it is on. */
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#define _FPU_DEFAULT 0x00001000 /* Default value. */
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#define _FPU_IEEE 0x001f1000 /* Default + exceptions enabled. */
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/* Type of the control word. */
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typedef unsigned int fpu_control_t;
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/* Macros for accessing the hardware control word. */
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#define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw))
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#define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw))
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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#endif /* _FPU_CONTROL_H */
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