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I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 6694 files FOO. I then removed trailing white space from benchtests/bench-pthread-locks.c and iconvdata/tst-iconv-big5-hkscs-to-2ucs4.c, to work around this diagnostic from Savannah: remote: *** pre-commit check failed ... remote: *** error: lines with trailing whitespace found remote: error: hook declined to update refs/heads/master
281 lines
6.5 KiB
ArmAsm
281 lines
6.5 KiB
ArmAsm
/* Jump to a new context powerpc32 common.
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Copyright (C) 2005-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* This is the common implementation of setcontext for powerpc32.
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It not complete in itself should be included in to a framework that
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defines:
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__CONTEXT_FUNC_NAME
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and if appropriate:
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__CONTEXT_ENABLE_FPRS
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__CONTEXT_ENABLE_VRS
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Any architecture that implements the Vector unit is assumed to also
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implement the floating unit. */
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/* Stack frame offsets. */
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#define _FRAME_BACKCHAIN 0
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#define _FRAME_LR_SAVE 4
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#define _FRAME_PARM_SAVE1 8
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#define _FRAME_PARM_SAVE2 12
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#define _FRAME_PARM_SAVE3 16
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#define _FRAME_PARM_SAVE4 20
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#ifdef __CONTEXT_ENABLE_VRS
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.machine "altivec"
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#endif
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ENTRY(__CONTEXT_FUNC_NAME)
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mflr r0
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stwu r1,-16(r1)
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cfi_adjust_cfa_offset (16)
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stw r0,20(r1)
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cfi_offset (lr, _FRAME_LR_SAVE)
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stw r31,12(r1)
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cfi_offset(r31,-4)
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lwz r31,_UC_REGS_PTR(r3)
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/* Restore the signal mask */
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li r5,0
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addi r4,r3,_UC_SIGMASK
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li r3,SIG_SETMASK
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bl __sigprocmask@local
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cmpwi r3,0
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bne 3f /* L(error_exit) */
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#ifdef PIC
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mflr r8
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# define got_label GENERATE_GOT_LABEL (__CONTEXT_FUNC_NAME)
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SETUP_GOT_ACCESS(r7,got_label)
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addis r7,r7,_GLOBAL_OFFSET_TABLE_-got_label@ha
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addi r7,r7,_GLOBAL_OFFSET_TABLE_-got_label@l
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# ifdef SHARED
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lwz r7,_rtld_global_ro@got(r7)
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mtlr r8
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+LOWORD(r7)
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# else
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lwz r7,_dl_hwcap@got(r7)
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mtlr r8
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lwz r7,LOWORD(r7)
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# endif
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#else
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lis r7,(_dl_hwcap+LOWORD)@ha
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lwz r7,(_dl_hwcap+LOWORD)@l(r7)
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#endif
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#ifdef __CONTEXT_ENABLE_FPRS
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# ifdef __CONTEXT_ENABLE_VRS
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andis. r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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la r10,(_UC_VREGS)(r31)
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beq 2f /* L(has_no_vec) */
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lwz r0,(32*16)(r10)
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li r9,(32*16)
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cmpwi r0,0
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mtspr VRSAVE,r0
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beq 2f /* L(has_no_vec) */
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lvx v19,r9,r10
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la r9,(16)(r10)
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lvx v0,0,r10
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lvx v1,0,r9
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addi r10,r10,32
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addi r9,r9,32
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mtvscr v19
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lvx v2,0,r10
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lvx v3,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v4,0,r10
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lvx v5,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v6,0,r10
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lvx v7,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v8,0,r10
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lvx v9,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v10,0,r10
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lvx v11,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v12,0,r10
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lvx v13,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v14,0,r10
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lvx v15,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v16,0,r10
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lvx v17,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v18,0,r10
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lvx v19,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v20,0,r10
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lvx v21,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v22,0,r10
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lvx v23,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v24,0,r10
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lvx v25,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v26,0,r10
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lvx v27,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v28,0,r10
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lvx v29,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v30,0,r10
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lvx v31,0,r9
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addi r10,r10,32
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addi r9,r9,32
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lvx v10,0,r10
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lvx v11,0,r9
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2: /* L(has_no_vec): */
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# endif /* __CONTEXT_ENABLE_VRS */
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/* Restore the floating-point registers */
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lfd fp31,_UC_FREGS+(32*8)(r31)
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lfd fp0,_UC_FREGS+(0*8)(r31)
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp31,1,0
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# else
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.machine push
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.machine "power6"
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r7,PPC_FEATURE_HAS_DFP
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beq 7f
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp31,1,0
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b 8f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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7: mtfsf 0xff,fp31
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8: .machine pop
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# endif /* _ARCH_PWR6 */
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lfd fp1,_UC_FREGS+(1*8)(r31)
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lfd fp2,_UC_FREGS+(2*8)(r31)
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lfd fp3,_UC_FREGS+(3*8)(r31)
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lfd fp4,_UC_FREGS+(4*8)(r31)
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lfd fp5,_UC_FREGS+(5*8)(r31)
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lfd fp6,_UC_FREGS+(6*8)(r31)
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lfd fp7,_UC_FREGS+(7*8)(r31)
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lfd fp8,_UC_FREGS+(8*8)(r31)
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lfd fp9,_UC_FREGS+(9*8)(r31)
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lfd fp10,_UC_FREGS+(10*8)(r31)
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lfd fp11,_UC_FREGS+(11*8)(r31)
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lfd fp12,_UC_FREGS+(12*8)(r31)
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lfd fp13,_UC_FREGS+(13*8)(r31)
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lfd fp14,_UC_FREGS+(14*8)(r31)
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lfd fp15,_UC_FREGS+(15*8)(r31)
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lfd fp16,_UC_FREGS+(16*8)(r31)
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lfd fp17,_UC_FREGS+(17*8)(r31)
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lfd fp18,_UC_FREGS+(18*8)(r31)
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lfd fp19,_UC_FREGS+(19*8)(r31)
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lfd fp20,_UC_FREGS+(20*8)(r31)
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lfd fp21,_UC_FREGS+(21*8)(r31)
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lfd fp22,_UC_FREGS+(22*8)(r31)
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lfd fp23,_UC_FREGS+(23*8)(r31)
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lfd fp24,_UC_FREGS+(24*8)(r31)
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lfd fp25,_UC_FREGS+(25*8)(r31)
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lfd fp26,_UC_FREGS+(26*8)(r31)
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lfd fp27,_UC_FREGS+(27*8)(r31)
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lfd fp28,_UC_FREGS+(28*8)(r31)
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lfd fp29,_UC_FREGS+(29*8)(r31)
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lfd fp30,_UC_FREGS+(30*8)(r31)
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lfd fp31,_UC_FREGS+(31*8)(r31)
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#endif /* __CONTEXT_ENABLE_FPRS */
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/* Restore LR and CCR, and set CTR to the NIP value */
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lwz r3,_UC_GREGS+(PT_LNK*4)(r31)
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lwz r4,_UC_GREGS+(PT_NIP*4)(r31)
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lwz r5,_UC_GREGS+(PT_CCR*4)(r31)
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mtlr r3
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mtctr r4
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mtcr r5
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/* Restore the general registers */
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lwz r1,_UC_GREGS+(PT_R1*4)(r31)
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lwz r3,_UC_GREGS+(PT_R3*4)(r31)
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lwz r4,_UC_GREGS+(PT_R4*4)(r31)
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lwz r5,_UC_GREGS+(PT_R5*4)(r31)
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lwz r6,_UC_GREGS+(PT_R6*4)(r31)
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lwz r7,_UC_GREGS+(PT_R7*4)(r31)
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lwz r8,_UC_GREGS+(PT_R8*4)(r31)
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lwz r9,_UC_GREGS+(PT_R9*4)(r31)
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lwz r10,_UC_GREGS+(PT_R10*4)(r31)
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lwz r11,_UC_GREGS+(PT_R11*4)(r31)
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lwz r12,_UC_GREGS+(PT_R12*4)(r31)
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lwz r13,_UC_GREGS+(PT_R13*4)(r31)
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lwz r14,_UC_GREGS+(PT_R14*4)(r31)
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lwz r15,_UC_GREGS+(PT_R15*4)(r31)
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lwz r16,_UC_GREGS+(PT_R16*4)(r31)
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lwz r17,_UC_GREGS+(PT_R17*4)(r31)
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lwz r18,_UC_GREGS+(PT_R18*4)(r31)
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lwz r19,_UC_GREGS+(PT_R19*4)(r31)
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lwz r20,_UC_GREGS+(PT_R20*4)(r31)
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lwz r21,_UC_GREGS+(PT_R21*4)(r31)
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lwz r22,_UC_GREGS+(PT_R22*4)(r31)
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lwz r23,_UC_GREGS+(PT_R23*4)(r31)
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lwz r24,_UC_GREGS+(PT_R24*4)(r31)
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lwz r25,_UC_GREGS+(PT_R25*4)(r31)
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lwz r26,_UC_GREGS+(PT_R26*4)(r31)
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lwz r27,_UC_GREGS+(PT_R27*4)(r31)
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lwz r28,_UC_GREGS+(PT_R28*4)(r31)
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lwz r29,_UC_GREGS+(PT_R29*4)(r31)
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lwz r30,_UC_GREGS+(PT_R30*4)(r31)
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lwz r31,_UC_GREGS+(PT_R31*4)(r31)
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bctr
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3: /* L(error_exit): */
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lwz r31,12(r1)
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lwz r0,20(r1)
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addi r1,r1,16
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mtlr r0
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blr
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END (__CONTEXT_FUNC_NAME)
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