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I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 6694 files FOO. I then removed trailing white space from benchtests/bench-pthread-locks.c and iconvdata/tst-iconv-big5-hkscs-to-2ucs4.c, to work around this diagnostic from Savannah: remote: *** pre-commit check failed ... remote: *** error: lines with trailing whitespace found remote: error: hook declined to update refs/heads/master
201 lines
6.6 KiB
C
201 lines
6.6 KiB
C
/* Copyright (C) 1998-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _SYS_UCONTEXT_H
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#define _SYS_UCONTEXT_H 1
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#include <features.h>
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#include <bits/types/sigset_t.h>
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#include <bits/types/stack_t.h>
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#ifdef __USE_MISC
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# define __ctx(fld) fld
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#else
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# define __ctx(fld) __ ## fld
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#endif
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struct __ctx(pt_regs);
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#if __WORDSIZE == 32
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/* Number of general registers. */
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# define __NGREG 48
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# ifdef __USE_MISC
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# define NGREG __NGREG
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# endif
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/* Container for all general registers. */
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typedef unsigned long gregset_t[__NGREG];
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/* Container for floating-point registers and status */
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typedef struct _libc_fpstate
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{
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double __ctx(fpregs)[32];
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double __ctx(fpscr);
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unsigned int _pad[2];
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} fpregset_t;
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/* Container for Altivec/VMX registers and status.
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Needs to be aligned on a 16-byte boundary. */
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typedef struct _libc_vrstate
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{
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unsigned int __ctx(vrregs)[32][4];
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unsigned int __ctx(vrsave);
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unsigned int _pad[2];
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unsigned int __ctx(vscr);
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} vrregset_t;
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/* Context to describe whole processor state. */
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typedef struct
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{
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gregset_t __ctx(gregs);
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fpregset_t __ctx(fpregs);
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vrregset_t __ctx(vrregs) __attribute__((__aligned__(16)));
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} mcontext_t;
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#else
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/* For 64-bit kernels with Altivec support, a machine context is exactly
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* a sigcontext. For older kernel (without Altivec) the sigcontext matches
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* the mcontext upto but not including the v_regs field. For kernels that
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* don't set AT_HWCAP or return AT_HWCAP without PPC_FEATURE_HAS_ALTIVEC the
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* v_regs field may not exist and should not be referenced. The v_regs field
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* can be referenced safely only after verifying that PPC_FEATURE_HAS_ALTIVEC
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* is set in AT_HWCAP. */
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/* Number of general registers. */
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# define __NGREG 48 /* includes r0-r31, nip, msr, lr, etc. */
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# define __NFPREG 33 /* includes fp0-fp31 &fpscr. */
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# define __NVRREG 34 /* includes v0-v31, vscr, & vrsave in
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split vectors */
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# ifdef __USE_MISC
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# define NGREG __NGREG
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# define NFPREG __NFPREG
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# define NVRREG __NVRREG
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# endif
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typedef unsigned long gregset_t[__NGREG];
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typedef double fpregset_t[__NFPREG];
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/* Container for Altivec/VMX Vector Status and Control Register. Only 32-bits
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but can only be copied to/from a 128-bit vector register. So we allocated
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a whole quadword speedup save/restore. */
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typedef struct _libc_vscr
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{
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#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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unsigned int __pad[3];
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unsigned int __ctx(vscr_word);
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#else
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unsigned int __ctx(vscr_word);
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unsigned int __pad[3];
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#endif
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} vscr_t;
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/* Container for Altivec/VMX registers and status.
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Must to be aligned on a 16-byte boundary. */
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typedef struct _libc_vrstate
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{
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unsigned int __ctx(vrregs)[32][4];
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vscr_t __ctx(vscr);
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unsigned int __ctx(vrsave);
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unsigned int __pad[3];
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} vrregset_t __attribute__((__aligned__(16)));
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typedef struct {
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unsigned long __glibc_reserved[4];
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int __ctx(signal);
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int __pad0;
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unsigned long __ctx(handler);
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unsigned long __ctx(oldmask);
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struct __ctx(pt_regs) *__ctx(regs);
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gregset_t __ctx(gp_regs);
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fpregset_t __ctx(fp_regs);
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/*
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* To maintain compatibility with current implementations the sigcontext is
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* extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
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* followed by an unstructured (vmx_reserve) field of 69 doublewords. This
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* allows the array of vector registers to be quadword aligned independent of
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* the alignment of the containing sigcontext or ucontext. It is the
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* responsibility of the code setting the sigcontext to set this pointer to
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* either NULL (if this processor does not support the VMX feature) or the
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* address of the first quadword within the allocated (vmx_reserve) area.
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*
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* The pointer (v_regs) of vector type (elf_vrreg_t) is essentially
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* an array of 34 quadword entries. The entries with
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* indexes 0-31 contain the corresponding vector registers. The entry with
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* index 32 contains the vscr as the last word (offset 12) within the
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* quadword. This allows the vscr to be stored as either a quadword (since
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* it must be copied via a vector register to/from storage) or as a word.
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* The entry with index 33 contains the vrsave as the first word (offset 0)
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* within the quadword.
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*/
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vrregset_t *__ctx(v_regs);
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long __ctx(vmx_reserve)[__NVRREG+__NVRREG+1];
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} mcontext_t;
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#endif
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/* Userlevel context. */
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typedef struct ucontext_t
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{
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unsigned long int __ctx(uc_flags);
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struct ucontext_t *uc_link;
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stack_t uc_stack;
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#if __WORDSIZE == 32
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/*
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* These fields are set up this way to maximize source and
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* binary compatibility with code written for the old
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* ucontext_t definition, which didn't include space for the
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* registers.
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*
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* Different versions of the kernel have stored the registers on
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* signal delivery at different offsets from the ucontext struct.
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* Programs should thus use the uc_mcontext.uc_regs pointer to
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* find where the registers are actually stored. The registers
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* will be stored within the ucontext_t struct but not necessarily
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* at a fixed address. As a side-effect, this lets us achieve
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* 16-byte alignment for the register storage space if the
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* Altivec registers are to be saved, without requiring 16-byte
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* alignment on the whole ucontext_t.
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*
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* The uc_mcontext.regs field is included for source compatibility
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* with programs written against the older ucontext_t definition,
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* and its name should therefore not change. The uc_pad field
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* is for binary compatibility with programs compiled against the
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* old ucontext_t; it ensures that uc_mcontext.regs and uc_sigmask
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* are at the same offset as previously.
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*/
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int __glibc_reserved1[7];
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union __ctx(uc_regs_ptr) {
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struct __ctx(pt_regs) *__ctx(regs);
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mcontext_t *__ctx(uc_regs);
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} uc_mcontext;
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sigset_t uc_sigmask;
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/* last for extensibility */
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char __ctx(uc_reg_space)[sizeof (mcontext_t) + 12];
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#else /* 64-bit */
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sigset_t uc_sigmask;
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mcontext_t uc_mcontext; /* last for extensibility */
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#endif
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} ucontext_t;
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#undef __ctx
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#endif /* sys/ucontext.h */
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