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304b22d7f9
All ABIs, except alpha, powerpc, and x86_64, define it to atomic_full_barrier/__sync_synchronize, which can be mapped to __atomic_thread_fence (__ATOMIC_SEQ_CST) in most cases, with the exception of aarch64 (where the acquire fence is generated as 'dmb ishld' instead of 'dmb ish'). For s390x, it defaults to a memory barrier where __sync_synchronize emits a 'bcr 15,0' (which the manual describes as pipeline synchronization). For PowerPC, it allows the use of lwsync for additional chips (since _ARCH_PWR4 does not cover all chips that support it). Tested on aarch64-linux-gnu, where the acquire produces a different instruction that the current code. Co-authored-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com> Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/* Atomic operations. PowerPC Common version.
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Copyright (C) 2003-2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _POWERPC_ATOMIC_MACHINE_H
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#define _POWERPC_ATOMIC_MACHINE_H 1
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#if __WORDSIZE == 64
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# define __HAVE_64B_ATOMICS 1
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#else
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# define __HAVE_64B_ATOMICS 0
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#endif
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#define ATOMIC_EXCHANGE_USES_CAS 1
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/* Used on pthread_spin_{try}lock. */
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#define __ARCH_ACQ_INSTR "isync"
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#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
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# define MUTEX_HINT_ACQ ",1"
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# define MUTEX_HINT_REL ",0"
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#else
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# define MUTEX_HINT_ACQ
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# define MUTEX_HINT_REL
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#endif
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#ifdef _ARCH_PWR4
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/*
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* "light weight" sync can also be used for the release barrier.
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*/
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# define atomic_write_barrier() __asm ("lwsync" ::: "memory")
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#else
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# define atomic_write_barrier() __asm ("sync" ::: "memory")
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#endif
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#endif
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