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Any FPU_STATUS write needs setting the FWE bit (31) whcih just provides a "control signal" to enable explicit write (vs. the side-effect of FPU instructions). However this bit is RAZ and write-only, thus effectively never stored in FPU_STATUS register. Thus when reading the register there is no need to clear it. This shaves off a BCLR instruction from the fe*exceptino family of functions and while no big deal still makes sense to do. This came up when debugging a race in math/test-fenv-tls [1] [1]: https://github.com/foss-for-synopsys-dwc-arc-processors/linux/issues/54 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
106 lines
3.7 KiB
C
106 lines
3.7 KiB
C
/* FPU control word bits. ARC version.
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Copyright (C) 2020-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _FPU_CONTROL_H
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#define _FPU_CONTROL_H
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/* ARC FPU control register bits.
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[ 0] -> IVE: Enable invalid operation exception.
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if 0, soft exception: status register IV flag set.
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if 1, hardware exception trap (not supported in Linux yet).
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[ 1] -> DZE: Enable division by zero exception.
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if 0, soft exception: status register IV flag set.
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if 1, hardware exception: (not supported in Linux yet).
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[9:8] -> RM: Rounding Mode:
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00 - Rounding toward zero.
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01 - Rounding to nearest (default).
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10 - Rounding (up) toward plus infinity.
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11 - Rounding (down)toward minus infinity.
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ARC FPU status register bits.
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[ 0] -> IV: flag invalid operation.
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[ 1] -> DZ: flag division by zero.
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[ 2] -> OV: flag Overflow operation.
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[ 3] -> UV: flag Underflow operation.
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[ 4] -> IX: flag Inexact operation.
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[31] -> FWE: Flag Write Enable.
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If 1, above flags writable explicitly (clearing),
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else IoW and only writable indirectly via bits [12:7]. */
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#include <features.h>
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#if !defined(__ARC_FPU_SP__) && !defined(__ARC_FPU_DP__)
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# define _FPU_RESERVED 0xffffffff
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# define _FPU_DEFAULT 0x00000000
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typedef unsigned int fpu_control_t;
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# define _FPU_GETCW(cw) (cw) = 0
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# define _FPU_SETCW(cw) (void) (cw)
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# define _FPU_GETS(cw) (cw) = 0
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# define _FPU_SETS(cw) (void) (cw)
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extern fpu_control_t __fpu_control;
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#else
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#define _FPU_RESERVED 0
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/* The fdlibm code requires strict IEEE double precision arithmetic,
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and no interrupts for exceptions, rounding to nearest.
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So only RM set to b'01. */
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# define _FPU_DEFAULT 0x00000100
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/* Actually default needs to have FWE bit as 1 but that is already
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ingrained into _FPU_SETS macro below. */
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#define _FPU_FPSR_DEFAULT 0x00000000
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#define __FPU_RND_SHIFT 8
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#define __FPU_RND_MASK 0x3
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/* Type of the control word. */
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typedef unsigned int fpu_control_t;
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/* Macros for accessing the hardware control word. */
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# define _FPU_GETCW(cw) __asm__ volatile ("lr %0, [0x300]" : "=r" (cw))
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# define _FPU_SETCW(cw) __asm__ volatile ("sr %0, [0x300]" : : "r" (cw))
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/* Macros for accessing the hardware status word.
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Writing to FPU_STATUS requires a "control" bit FWE to be able to set the
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exception flags directly (as opposed to side-effects of FP instructions).
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That is done in the macro here to keeps callers agnostic of this detail.
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And given FWE is write-only and RAZ, no need to "clear" it in _FPU_GETS
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macro. */
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# define _FPU_GETS(cw) \
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__asm__ volatile ("lr %0, [0x301] \r\n" \
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: "=r" (cw))
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# define _FPU_SETS(cw) \
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do { \
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unsigned int __fwe = 0x80000000 | (cw); \
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__asm__ volatile ("sr %0, [0x301] \r\n" \
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: : "r" (__fwe)); \
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} while (0)
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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#endif
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#endif /* fpu_control.h */
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