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99c7f8700d
Handle prelinked libraries and binaries with new style PLT. 2005-06-07 Jakub Jelinek <jakub@redhat.com> * elf/elf.h (R_PPC_REL16, R_PPC_REL16_LO, R_PPC_REL16_HI, R_PPC_REL16_HA): Define. 2005-06-14 Alan Modra <amodra@bigpond.net.au> * config.h.in (HAVE_ASM_PPC_REL16): Add. * elf/elf.h (DT_PPC_GOT, DT_PPC_NUM): Define. * elf/tls-macros.h (PowerPC32): Include config.h. Add variants of TLS_IE, TLS_LD and TLS_GD for new PLT/GOT layout. * sysdeps/powerpc/powerpc32/configure.in: New file, * sysdeps/powerpc/powerpc32/dl-dtprocnum.h: New file. * sysdeps/powerpc/powerpc32/dl-machine.h (DT_PPC): Define. (ppc_got): New inline function. (elf_machine_dynamic): Use ppc_got. Add attribute const. (elf_machine_load_address): Add attribute const. Don't use int vars. Use bcl rather than bl to save trashing branch target stack. Use elf_machine_dynamic rather than duplicating code here. (elf_machine_runtime_setup): New inline function replacing define. Handle new PLT. (elf_machine_fixup_plt): Handle new PLT. (elf_machine_rela): Likewise. * sysdeps/powerpc/powerpc32/sysdep.h: Include config.h. (CALL_MCOUNT): Don't set up counter vars. * sysdeps/powerpc/powerpc32/ppc-mcount.S: Correct comment. * sysdeps/powerpc/powerpc32/elf/start.S (start_addressesp): Don't define when HAVE_ASM_PPC_REL16. (_start): Add HAVE_ASM_PPC_REL16 code. * sysdeps/powerpc/powerpc32/dl-start.S (_dl_start_user): Don't bl into the GOT when HAVE_ASM_PPC_REL16. * sysdeps/powerpc/powerpc32/memset.S (memset): Likewise. * sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S (__longjmp): Ditto. * sysdeps/powerpc/powerpc32/fpu/s_ceil.S (__ceil): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_ceilf.S (__ceilf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_floor.S (__floor): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_floorf.S (__floorf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_lround.S (__lround): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_rint.S (__rint): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_rintf.S (__rintf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_round.S (__round): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_roundf.S (__roundf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_trunc.S (__trunc): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_truncf.S (__truncf): Likewise. * sysdeps/powerpc/powerpc32/fpu/setjmp-common.S (__sigsetjmp): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/brk.S (__brk): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S (__getcontext): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S (__setcontext): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S (__swapcontext): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/socket.S (stackblock): Comment. (__socket): Bomb if NARGS >= 7. Invoke CGOTSETUP and CGOTRESTORE. 2005-06-17 Ulrich Drepper <drepper@redhat.com> * sysdeps/posix/sigignore.c: Include <string.h> to tell the compiler to use __GI_memset. * sysdeps/posix/signal.c: Likewise. * sysdeps/posix/sigset.c: Likewise. * sysdeps/posix/sysv_signal.c: Likewise. * sysdeps/unix/sysv/linux/sleep.c: Likewise. * sysdeps/unix/sysv/linux/sysctl.c: Likewise. * sysdeps/unix/sysv/linux/system.c: Likewise.
401 lines
10 KiB
ArmAsm
401 lines
10 KiB
ArmAsm
/* Save current context.
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Copyright (C) 2002, 2004 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#include <sysdep.h>
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#include <rtld-global-offsets.h>
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#include <shlib-compat.h>
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#define __ASSEMBLY__
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#include <asm/ptrace.h>
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#include "ucontext_i.h"
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.machine "altivec"
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ENTRY(__getcontext)
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stwu r1,-16(r1)
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/* Insure that the _UC_REGS start on a quadword boundary. */
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stw r3,_FRAME_PARM_SAVE1(r1)
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addi r3,r3,_UC_REG_SPACE+12
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clrrwi r3,r3,4
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/* Save the general purpose registers */
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stw r0,_UC_GREGS+(PT_R0*4)(r3)
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mflr r0
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stw r2,_UC_GREGS+(PT_R2*4)(r3)
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stw r4,_UC_GREGS+(PT_R4*4)(r3)
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/* Set the callers LR_SAVE, and the ucontext LR and NIP to the callers
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return address. */
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stw r0,_UC_GREGS+(PT_LNK*4)(r3)
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stw r0,_UC_GREGS+(PT_NIP*4)(r3)
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stw r0,_FRAME_LR_SAVE+16(r1)
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stw r5,_UC_GREGS+(PT_R5*4)(r3)
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stw r6,_UC_GREGS+(PT_R6*4)(r3)
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stw r7,_UC_GREGS+(PT_R7*4)(r3)
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stw r8,_UC_GREGS+(PT_R8*4)(r3)
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stw r9,_UC_GREGS+(PT_R9*4)(r3)
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stw r10,_UC_GREGS+(PT_R10*4)(r3)
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stw r11,_UC_GREGS+(PT_R11*4)(r3)
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stw r12,_UC_GREGS+(PT_R12*4)(r3)
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stw r13,_UC_GREGS+(PT_R13*4)(r3)
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stw r14,_UC_GREGS+(PT_R14*4)(r3)
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stw r15,_UC_GREGS+(PT_R15*4)(r3)
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stw r16,_UC_GREGS+(PT_R16*4)(r3)
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stw r17,_UC_GREGS+(PT_R17*4)(r3)
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stw r18,_UC_GREGS+(PT_R18*4)(r3)
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stw r19,_UC_GREGS+(PT_R19*4)(r3)
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stw r20,_UC_GREGS+(PT_R20*4)(r3)
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stw r21,_UC_GREGS+(PT_R21*4)(r3)
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stw r22,_UC_GREGS+(PT_R22*4)(r3)
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stw r23,_UC_GREGS+(PT_R23*4)(r3)
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stw r24,_UC_GREGS+(PT_R24*4)(r3)
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stw r25,_UC_GREGS+(PT_R25*4)(r3)
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stw r26,_UC_GREGS+(PT_R26*4)(r3)
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stw r27,_UC_GREGS+(PT_R27*4)(r3)
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stw r28,_UC_GREGS+(PT_R28*4)(r3)
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stw r29,_UC_GREGS+(PT_R29*4)(r3)
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stw r30,_UC_GREGS+(PT_R30*4)(r3)
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stw r31,_UC_GREGS+(PT_R31*4)(r3)
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/* Save the value of R1. We had to push the stack before we
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had the address of uc_reg_space. So compute the address of
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the callers stack pointer and save it as R1. */
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addi r8,r1,16
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li r0,0
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/* Save the count, exception and condition registers. */
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mfctr r11
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mfxer r10
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mfcr r9
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stw r8,_UC_GREGS+(PT_R1*4)(r3)
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stw r11,_UC_GREGS+(PT_CTR*4)(r3)
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stw r10,_UC_GREGS+(PT_XER*4)(r3)
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stw r9,_UC_GREGS+(PT_CCR*4)(r3)
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/* Set the return value of getcontext to "success". R3 is the only
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register whose value is not preserved in the saved context. */
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stw r0,_UC_GREGS+(PT_R3*4)(r3)
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/* Zero fill fields that can't be set in user state. */
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stw r0,_UC_GREGS+(PT_MSR*4)(r3)
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stw r0,_UC_GREGS+(PT_MQ*4)(r3)
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/* Save the floating-point registers */
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stfd fp0,_UC_FREGS+(0*8)(r3)
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stfd fp1,_UC_FREGS+(1*8)(r3)
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stfd fp2,_UC_FREGS+(2*8)(r3)
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stfd fp3,_UC_FREGS+(3*8)(r3)
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stfd fp4,_UC_FREGS+(4*8)(r3)
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stfd fp5,_UC_FREGS+(5*8)(r3)
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stfd fp6,_UC_FREGS+(6*8)(r3)
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stfd fp7,_UC_FREGS+(7*8)(r3)
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stfd fp8,_UC_FREGS+(8*8)(r3)
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stfd fp9,_UC_FREGS+(9*8)(r3)
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stfd fp10,_UC_FREGS+(10*8)(r3)
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stfd fp11,_UC_FREGS+(11*8)(r3)
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stfd fp12,_UC_FREGS+(12*8)(r3)
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stfd fp13,_UC_FREGS+(13*8)(r3)
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stfd fp14,_UC_FREGS+(14*8)(r3)
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stfd fp15,_UC_FREGS+(15*8)(r3)
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stfd fp16,_UC_FREGS+(16*8)(r3)
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stfd fp17,_UC_FREGS+(17*8)(r3)
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stfd fp18,_UC_FREGS+(18*8)(r3)
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stfd fp19,_UC_FREGS+(19*8)(r3)
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stfd fp20,_UC_FREGS+(20*8)(r3)
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stfd fp21,_UC_FREGS+(21*8)(r3)
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stfd fp22,_UC_FREGS+(22*8)(r3)
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stfd fp23,_UC_FREGS+(23*8)(r3)
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stfd fp24,_UC_FREGS+(24*8)(r3)
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stfd fp25,_UC_FREGS+(25*8)(r3)
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stfd fp26,_UC_FREGS+(26*8)(r3)
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stfd fp27,_UC_FREGS+(27*8)(r3)
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stfd fp28,_UC_FREGS+(28*8)(r3)
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stfd fp29,_UC_FREGS+(29*8)(r3)
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mffs fp0
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stfd fp30,_UC_FREGS+(30*8)(r3)
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stfd fp31,_UC_FREGS+(31*8)(r3)
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stfd fp0,_UC_FREGS+(32*8)(r3)
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#ifdef PIC
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mflr r8
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# ifdef HAVE_ASM_PPC_REL16
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bcl 20,31,1f
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1: mflr r7
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addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
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addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
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# else
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bl _GLOBAL_OFFSET_TABLE_@local-4
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mflr r7
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# endif
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# ifdef SHARED
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lwz r7,_rtld_global_ro@got(r7)
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mtlr r8
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
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# else
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lwz r7,_dl_hwcap@got(r7)
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mtlr r8
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lwz r7,0(r7)
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# endif
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#else
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lis r7,_dl_hwcap@ha
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lwz r7,_dl_hwcap@l(r7)
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#endif
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andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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la r10,(_UC_VREGS)(r3)
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la r9,(_UC_VREGS+16)(r3)
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beq L(no_vec)
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/* address of the combined VSCR/VSAVE quadword. */
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la r8,(_UC_VREGS+512)(r3)
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/* Save the vector registers */
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stvx v0,0,r10
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stvx v1,0,r9
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addi r10,r10,32
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addi r9,r9,32
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/* We need to get the Vector Status and Control Register early to avoid
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store order problems later with the VSAVE register that shares the
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same quadword. */
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mfvscr v0
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stvx v2,0,r10
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stvx v3,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v0,0,r8
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stvx v4,0,r10
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stvx v5,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v6,0,r10
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stvx v7,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v8,0,r10
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stvx v9,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v10,0,r10
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stvx v11,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v12,0,r10
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stvx v13,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v14,0,r10
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stvx v15,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v16,0,r10
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stvx v17,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v18,0,r10
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stvx v19,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v20,0,r10
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stvx v21,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v22,0,r10
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stvx v23,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v24,0,r10
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stvx v25,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v26,0,r10
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stvx v27,0,r9
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addi r10,r10,32
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addi r9,r9,32
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stvx v28,0,r10
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stvx v29,0,r9
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addi r10,r10,32
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addi r9,r9,32
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mfspr r0,VRSAVE
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stvx v30,0,r10
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stvx v31,0,r9
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stw r0,0(r8)
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L(no_vec):
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/* We need to set up parms and call sigprocmask which will clobber
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volatile registers. So before the call we need to retrieve the
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original ucontext ptr (parm1) from stack and store the UC_REGS_PTR
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(current R3). */
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lwz r12,_FRAME_PARM_SAVE1(r1)
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li r4,0
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stw r3,_UC_REGS_PTR(r12)
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addi r5,r12,_UC_SIGMASK
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li r3,SIG_BLOCK
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bl __sigprocmask@local
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lwz r0,_FRAME_LR_SAVE+16(r1)
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addi r1,r1,16
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mtlr r0
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blr
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END(__getcontext)
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versioned_symbol (libc, __getcontext, getcontext, GLIBC_2_3_4)
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#if SHLIB_COMPAT (libc, GLIBC_2_3_3, GLIBC_2_3_4)
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compat_text_section
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ENTRY(__novec_getcontext)
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/*
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* Since we are not attempting to save the altivec registers,
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* there is no need to get the register storage space
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* aligned on a 16-byte boundary.
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*/
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addi r3,r3,_UC_REG_SPACE
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stw r3,_UC_REGS_PTR - _UC_REG_SPACE(r3)
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stw r0,_UC_GREGS+(PT_R0*4)(r3)
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stw r1,_UC_GREGS+(PT_R1*4)(r3)
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mflr r0
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stwu r1,-16(r1)
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stw r0,20(r1)
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stw r0,_UC_GREGS+(PT_LNK*4)(r3)
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stw r0,_UC_GREGS+(PT_NIP*4)(r3)
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stw r2,_UC_GREGS+(PT_R2*4)(r3)
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stw r4,_UC_GREGS+(PT_R4*4)(r3)
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stw r5,_UC_GREGS+(PT_R5*4)(r3)
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stw r6,_UC_GREGS+(PT_R6*4)(r3)
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stw r7,_UC_GREGS+(PT_R7*4)(r3)
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stw r8,_UC_GREGS+(PT_R8*4)(r3)
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stw r9,_UC_GREGS+(PT_R9*4)(r3)
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stw r10,_UC_GREGS+(PT_R10*4)(r3)
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stw r11,_UC_GREGS+(PT_R11*4)(r3)
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stw r12,_UC_GREGS+(PT_R12*4)(r3)
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stw r13,_UC_GREGS+(PT_R13*4)(r3)
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stw r14,_UC_GREGS+(PT_R14*4)(r3)
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stw r15,_UC_GREGS+(PT_R15*4)(r3)
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stw r16,_UC_GREGS+(PT_R16*4)(r3)
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stw r17,_UC_GREGS+(PT_R17*4)(r3)
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stw r18,_UC_GREGS+(PT_R18*4)(r3)
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stw r19,_UC_GREGS+(PT_R19*4)(r3)
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stw r20,_UC_GREGS+(PT_R20*4)(r3)
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stw r21,_UC_GREGS+(PT_R21*4)(r3)
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stw r22,_UC_GREGS+(PT_R22*4)(r3)
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stw r23,_UC_GREGS+(PT_R23*4)(r3)
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stw r24,_UC_GREGS+(PT_R24*4)(r3)
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stw r25,_UC_GREGS+(PT_R25*4)(r3)
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stw r26,_UC_GREGS+(PT_R26*4)(r3)
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stw r27,_UC_GREGS+(PT_R27*4)(r3)
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stw r28,_UC_GREGS+(PT_R28*4)(r3)
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stw r29,_UC_GREGS+(PT_R29*4)(r3)
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stw r30,_UC_GREGS+(PT_R30*4)(r3)
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stw r31,_UC_GREGS+(PT_R31*4)(r3)
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mfctr r0
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stw r0,_UC_GREGS+(PT_CTR*4)(r3)
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mfxer r0
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stw r0,_UC_GREGS+(PT_XER*4)(r3)
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mfcr r0
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stw r0,_UC_GREGS+(PT_CCR*4)(r3)
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/* Set the return value of getcontext to "success". R3 is the only
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register whose value is not preserved in the saved context. */
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li r0,0
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stw r0,_UC_GREGS+(PT_R3*4)(r3)
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/* Zero fill fields that can't be set in user state. */
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stw r0,_UC_GREGS+(PT_MSR*4)(r3)
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stw r0,_UC_GREGS+(PT_MQ*4)(r3)
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/* Save the floating-point registers */
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stfd fp0,_UC_FREGS+(0*8)(r3)
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stfd fp1,_UC_FREGS+(1*8)(r3)
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stfd fp2,_UC_FREGS+(2*8)(r3)
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stfd fp3,_UC_FREGS+(3*8)(r3)
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stfd fp4,_UC_FREGS+(4*8)(r3)
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stfd fp5,_UC_FREGS+(5*8)(r3)
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stfd fp6,_UC_FREGS+(6*8)(r3)
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stfd fp7,_UC_FREGS+(7*8)(r3)
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stfd fp8,_UC_FREGS+(8*8)(r3)
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stfd fp9,_UC_FREGS+(9*8)(r3)
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stfd fp10,_UC_FREGS+(10*8)(r3)
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stfd fp11,_UC_FREGS+(11*8)(r3)
|
|
stfd fp12,_UC_FREGS+(12*8)(r3)
|
|
stfd fp13,_UC_FREGS+(13*8)(r3)
|
|
stfd fp14,_UC_FREGS+(14*8)(r3)
|
|
stfd fp15,_UC_FREGS+(15*8)(r3)
|
|
stfd fp16,_UC_FREGS+(16*8)(r3)
|
|
stfd fp17,_UC_FREGS+(17*8)(r3)
|
|
stfd fp18,_UC_FREGS+(18*8)(r3)
|
|
stfd fp19,_UC_FREGS+(19*8)(r3)
|
|
stfd fp20,_UC_FREGS+(20*8)(r3)
|
|
stfd fp21,_UC_FREGS+(21*8)(r3)
|
|
stfd fp22,_UC_FREGS+(22*8)(r3)
|
|
stfd fp23,_UC_FREGS+(23*8)(r3)
|
|
stfd fp24,_UC_FREGS+(24*8)(r3)
|
|
stfd fp25,_UC_FREGS+(25*8)(r3)
|
|
stfd fp26,_UC_FREGS+(26*8)(r3)
|
|
stfd fp27,_UC_FREGS+(27*8)(r3)
|
|
stfd fp28,_UC_FREGS+(28*8)(r3)
|
|
stfd fp29,_UC_FREGS+(29*8)(r3)
|
|
mffs fp0
|
|
stfd fp30,_UC_FREGS+(30*8)(r3)
|
|
stfd fp31,_UC_FREGS+(31*8)(r3)
|
|
stfd fp0,_UC_FREGS+(32*8)(r3)
|
|
|
|
addi r5,r3,_UC_SIGMASK - _UC_REG_SPACE
|
|
li r4,0
|
|
li r3,SIG_BLOCK
|
|
bl __sigprocmask@local
|
|
|
|
lwz r0,20(r1)
|
|
addi r1,r1,16
|
|
mtlr r0
|
|
blr
|
|
END(__novec_getcontext)
|
|
.previous
|
|
|
|
compat_symbol (libc, __novec_getcontext, getcontext, GLIBC_2_3_3)
|
|
|
|
#endif
|
|
|
|
#if SHLIB_COMPAT (libc, GLIBC_2_1, GLIBC_2_3_3)
|
|
|
|
#define _ERRNO_H 1
|
|
#include <bits/errno.h>
|
|
|
|
compat_text_section
|
|
ENTRY (__getcontext_stub)
|
|
li r3,ENOSYS
|
|
b __syscall_error@local
|
|
END (__getcontext_stub)
|
|
.previous
|
|
|
|
compat_symbol (libc, __getcontext_stub, getcontext, GLIBC_2_1)
|
|
|
|
#endif
|