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fc2ba8037d
Phecda is HXT semiconductor's CPU core, this patch adds memory operation ifuncs for it: sharing the same optimized implementation with Qualcomm's Falkor core. 2018-06-07 Minfeng Kang <minfeng.kang@hxt-semitech.com> Hongbo Zhang <hongbo.zhang@linaro.org> * sysdeps/aarch64/multiarch/memcpy.c (libc_ifunc): reuse __memcpy_falkor for phecda core. * sysdeps/aarch64/multiarch/memmove.c (libc_ifunc): reuse __memmove_falkor for phecda core. * sysdeps/aarch64/multiarch/memset.c (libc_ifunc): reuse __memset_falkor for phecda core. * sysdeps/unix/sysv/linux/aarch64/cpu-features.c: add MIDR entry for phecda core. * sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_PHECDA): add macro to identify phecda core.
62 lines
2.3 KiB
C
62 lines
2.3 KiB
C
/* Initialize CPU feature data. AArch64 version.
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This file is part of the GNU C Library.
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Copyright (C) 2017-2018 Free Software Foundation, Inc.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _CPU_FEATURES_AARCH64_H
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#define _CPU_FEATURES_AARCH64_H
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#include <stdint.h>
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#define MIDR_PARTNUM_SHIFT 4
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#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
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#define MIDR_PARTNUM(midr) \
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(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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#define MIDR_ARCHITECTURE_SHIFT 16
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#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_ARCHITECTURE(midr) \
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(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_VARIANT_SHIFT 20
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#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
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#define MIDR_VARIANT(midr) \
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(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
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#define MIDR_IMPLEMENTOR_SHIFT 24
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#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_IMPLEMENTOR(midr) \
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(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
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#define IS_THUNDERX(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \
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&& MIDR_PARTNUM(midr) == 0x0a1)
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#define IS_THUNDERX2PA(midr) (MIDR_IMPLEMENTOR(midr) == 'B' \
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&& MIDR_PARTNUM(midr) == 0x516)
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#define IS_THUNDERX2(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \
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&& MIDR_PARTNUM(midr) == 0xaf)
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#define IS_FALKOR(midr) (MIDR_IMPLEMENTOR(midr) == 'Q' \
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&& MIDR_PARTNUM(midr) == 0xc00)
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#define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \
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&& MIDR_PARTNUM(midr) == 0x000)
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struct cpu_features
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{
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uint64_t midr_el1;
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unsigned zva_size;
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};
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#endif /* _CPU_FEATURES_AARCH64_H */
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