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4c966c0780
Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb extension. With special `-march` flags defined, we can generate more simplified code compared to the generic implementation of `ffs`/`ffsll`. Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn> Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
11 lines
292 B
C
11 lines
292 B
C
#if __GNUC_PREREQ (12, 0) && defined __riscv_zbb
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# define USE_FFS_BUILTIN 1
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# define USE_FFSLL_BUILTIN 1
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#elif __GNUC_PREREQ (13, 0) && defined __riscv_xtheadbb
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# define USE_FFS_BUILTIN 0
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# define USE_FFSLL_BUILTIN 1
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#else
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# define USE_FFS_BUILTIN 0
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# define USE_FFSLL_BUILTIN 0
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#endif
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