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b990b0aee2
Now we finally support modern GCC and binutils, it's time for a cleanup. Remove HAVE_AARCH64_SVE_ASM define and conditional compilation. Remove SVE configure checks for SVE, ACLE and variant-PCS support. Reviewed-by: Yury Khrustalev <yury.khrustalev@arm.com>
121 lines
2.6 KiB
ArmAsm
121 lines
2.6 KiB
ArmAsm
/* Optimized memset for SVE.
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Copyright (C) 2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD, SVE, unaligned accesses.
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* ZVA size is 64.
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*/
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.arch armv8.2-a+sve
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#define dstin x0
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#define val x1
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#define valw w1
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#define count x2
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#define dst x3
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#define dstend x4
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#define zva_val x5
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#define vlen x5
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#define off x3
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#define dstend2 x5
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ENTRY (__memset_sve_zva64)
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dup v0.16B, valw
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cmp count, 16
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b.lo L(set_16)
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add dstend, dstin, count
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cmp count, 64
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b.hs L(set_128)
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/* Set 16..63 bytes. */
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mov off, 16
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and off, off, count, lsr 1
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sub dstend2, dstend, off
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str q0, [dstin]
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str q0, [dstin, off]
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str q0, [dstend2, -16]
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str q0, [dstend, -16]
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ret
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.p2align 4
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L(set_16):
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whilelo p0.b, xzr, count
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st1b z0.b, p0, [dstin]
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ret
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.p2align 4
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L(set_128):
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bic dst, dstin, 15
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cmp count, 128
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b.hi L(set_long)
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stp q0, q0, [dstin]
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stp q0, q0, [dstin, 32]
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 4
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L(set_long):
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cmp count, 256
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b.lo L(no_zva)
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tst valw, 255
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b.ne L(no_zva)
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str q0, [dstin]
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str q0, [dst, 16]
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bic dst, dstin, 31
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stp q0, q0, [dst, 32]
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bic dst, dstin, 63
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sub count, dstend, dst /* Count is now 64 too large. */
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sub count, count, 128 /* Adjust count and bias for loop. */
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sub x8, dstend, 1 /* Write last bytes before ZVA loop. */
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bic x8, x8, 15
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stp q0, q0, [x8, -48]
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str q0, [x8, -16]
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str q0, [dstend, -16]
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.p2align 4
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L(zva64_loop):
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add dst, dst, 64
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dc zva, dst
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subs count, count, 64
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b.hi L(zva64_loop)
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ret
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L(no_zva):
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str q0, [dstin]
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sub count, dstend, dst /* Count is 16 too large. */
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sub count, count, 64 + 16 /* Adjust count and bias for loop. */
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L(no_zva_loop):
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stp q0, q0, [dst, 16]
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stp q0, q0, [dst, 48]
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add dst, dst, 64
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subs count, count, 64
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b.hi L(no_zva_loop)
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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END (__memset_sve_zva64)
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