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<sys/platform/x86.h>: Remove the C preprocessor magic
In <sys/platform/x86.h>, define CPU features as enum instead of using the C preprocessor magic to make it easier to wrap this functionality in other languages. Move the C preprocessor magic to internal header for better GCC codegen when more than one features are checked in a single expression as in x86-64 dl-hwcaps-subdirs.c. 1. Rename COMMON_CPUID_INDEX_XXX to CPUID_INDEX_XXX. 2. Move CPUID_INDEX_MAX to sysdeps/x86/include/cpu-features.h. 3. Remove struct cpu_features and __x86_get_cpu_features from <sys/platform/x86.h>. 4. Add __x86_get_cpuid_feature_leaf to <sys/platform/x86.h> and put it in libc. 5. Make __get_cpu_features() private to glibc. 6. Replace __x86_get_cpu_features(N) with __get_cpu_features(). 7. Add _dl_x86_get_cpu_features to GLIBC_PRIVATE. 8. Use a single enum index for each CPU feature detection. 9. Pass the CPUID feature leaf to __x86_get_cpuid_feature_leaf. 10. Return zero struct cpuid_feature for the older glibc binary with a smaller CPUID_INDEX_MAX [BZ #27104]. 11. Inside glibc, use the C preprocessor magic so that cpu_features data can be loaded just once leading to more compact code for glibc. 256 bits are used for each CPUID leaf. Some leaves only contain a few features. We can add exceptions to such leaves. But it will increase code sizes and it is harder to provide backward/forward compatibilities when new features are added to such leaves in the future. When new leaves are added, _rtld_global_ro offsets will change which leads to race condition during in-place updates. We may avoid in-place updates by 1. Rename the old glibc. 2. Install the new glibc. 3. Remove the old glibc. NB: A function, __x86_get_cpuid_feature_leaf , is used to avoid the copy relocation issue with IFUNC resolver as shown in IFUNC resolver tests.
This commit is contained in:
H.J. Lu
@ -19,760 +19,47 @@
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#ifndef _SYS_PLATFORM_X86_H
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#define _SYS_PLATFORM_X86_H
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enum
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#include <features.h>
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#include <stdbool.h>
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#include <bits/platform/x86.h>
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__BEGIN_DECLS
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/* Get a pointer to the CPU feature structure. */
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extern const struct cpuid_feature *__x86_get_cpuid_feature_leaf (unsigned int)
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__attribute__ ((pure));
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static __inline__ _Bool
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x86_cpu_has_feature (unsigned int __index)
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{
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COMMON_CPUID_INDEX_1 = 0,
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COMMON_CPUID_INDEX_7,
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COMMON_CPUID_INDEX_80000001,
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COMMON_CPUID_INDEX_D_ECX_1,
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COMMON_CPUID_INDEX_80000007,
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COMMON_CPUID_INDEX_80000008,
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COMMON_CPUID_INDEX_7_ECX_1,
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COMMON_CPUID_INDEX_19,
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/* Keep the following line at the end. */
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COMMON_CPUID_INDEX_MAX
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};
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const struct cpuid_feature *__ptr = __x86_get_cpuid_feature_leaf
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(__index / (8 * sizeof (unsigned int) * 4));
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unsigned int __reg
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= __index & (8 * sizeof (unsigned int) * 4 - 1);
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unsigned int __bit = __reg & (8 * sizeof (unsigned int) - 1);
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__reg /= 8 * sizeof (unsigned int);
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struct cpuid_registers
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return __ptr->cpuid_array[__reg] & (1 << __bit);
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}
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static __inline__ _Bool
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x86_cpu_is_usable (unsigned int __index)
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{
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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};
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const struct cpuid_feature *__ptr = __x86_get_cpuid_feature_leaf
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(__index / (8 * sizeof (unsigned int) * 4));
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unsigned int __reg
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= __index & (8 * sizeof (unsigned int) * 4 - 1);
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unsigned int __bit = __reg & (8 * sizeof (unsigned int) - 1);
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__reg /= 8 * sizeof (unsigned int);
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struct cpuid_features
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{
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struct cpuid_registers cpuid;
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struct cpuid_registers usable;
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};
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enum cpu_features_kind
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{
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arch_kind_unknown = 0,
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arch_kind_intel,
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arch_kind_amd,
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arch_kind_zhaoxin,
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arch_kind_other
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};
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struct cpu_features_basic
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{
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enum cpu_features_kind kind;
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int max_cpuid;
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unsigned int family;
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unsigned int model;
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unsigned int stepping;
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};
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struct cpu_features
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{
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struct cpu_features_basic basic;
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struct cpuid_features features[COMMON_CPUID_INDEX_MAX];
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};
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/* Get a pointer to the CPU features structure. */
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extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
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__attribute__ ((const));
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#define CPU_FEATURE_CHECK_P(ptr, name, check) \
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((ptr->features[index_cpu_##name].check.reg_##name \
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& bit_cpu_##name) != 0)
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#define CPU_FEATURE_CPU_P(ptr, name) \
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CPU_FEATURE_CHECK_P (ptr, name, cpuid)
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#define CPU_FEATURE_USABLE_P(ptr, name) \
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CPU_FEATURE_CHECK_P (ptr, name, usable)
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return __ptr->usable_array[__reg] & (1 << __bit);
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}
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/* HAS_CPU_FEATURE evaluates to true if CPU supports the feature. */
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#define HAS_CPU_FEATURE(name) \
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(__extension__ \
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({ const struct cpu_features *__ptr = \
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__x86_get_cpu_features (COMMON_CPUID_INDEX_MAX); \
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__ptr && CPU_FEATURE_CPU_P (__ptr, name); }))
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#define HAS_CPU_FEATURE(name) x86_cpu_has_feature (x86_cpu_##name)
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/* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
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#define CPU_FEATURE_USABLE(name) \
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(__extension__ \
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({ const struct cpu_features *__ptr = \
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__x86_get_cpu_features (COMMON_CPUID_INDEX_MAX); \
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__ptr && CPU_FEATURE_USABLE_P (__ptr, name); }))
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#define CPU_FEATURE_USABLE(name) x86_cpu_is_usable (x86_cpu_##name)
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/* CPU features. */
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/* COMMON_CPUID_INDEX_1. */
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/* ECX. */
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#define bit_cpu_SSE3 (1u << 0)
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#define bit_cpu_PCLMULQDQ (1u << 1)
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#define bit_cpu_DTES64 (1u << 2)
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#define bit_cpu_MONITOR (1u << 3)
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#define bit_cpu_DS_CPL (1u << 4)
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#define bit_cpu_VMX (1u << 5)
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#define bit_cpu_SMX (1u << 6)
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#define bit_cpu_EIST (1u << 7)
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#define bit_cpu_TM2 (1u << 8)
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#define bit_cpu_SSSE3 (1u << 9)
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#define bit_cpu_CNXT_ID (1u << 10)
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#define bit_cpu_SDBG (1u << 11)
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#define bit_cpu_FMA (1u << 12)
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#define bit_cpu_CMPXCHG16B (1u << 13)
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#define bit_cpu_XTPRUPDCTRL (1u << 14)
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#define bit_cpu_PDCM (1u << 15)
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#define bit_cpu_INDEX_1_ECX_16 (1u << 16)
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#define bit_cpu_PCID (1u << 17)
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#define bit_cpu_DCA (1u << 18)
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#define bit_cpu_SSE4_1 (1u << 19)
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#define bit_cpu_SSE4_2 (1u << 20)
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#define bit_cpu_X2APIC (1u << 21)
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#define bit_cpu_MOVBE (1u << 22)
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#define bit_cpu_POPCNT (1u << 23)
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#define bit_cpu_TSC_DEADLINE (1u << 24)
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#define bit_cpu_AES (1u << 25)
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#define bit_cpu_XSAVE (1u << 26)
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#define bit_cpu_OSXSAVE (1u << 27)
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#define bit_cpu_AVX (1u << 28)
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#define bit_cpu_F16C (1u << 29)
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#define bit_cpu_RDRAND (1u << 30)
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#define bit_cpu_INDEX_1_ECX_31 (1u << 31)
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/* EDX. */
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#define bit_cpu_FPU (1u << 0)
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#define bit_cpu_VME (1u << 1)
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#define bit_cpu_DE (1u << 2)
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#define bit_cpu_PSE (1u << 3)
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#define bit_cpu_TSC (1u << 4)
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#define bit_cpu_MSR (1u << 5)
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#define bit_cpu_PAE (1u << 6)
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#define bit_cpu_MCE (1u << 7)
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#define bit_cpu_CX8 (1u << 8)
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#define bit_cpu_APIC (1u << 9)
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#define bit_cpu_INDEX_1_EDX_10 (1u << 10)
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#define bit_cpu_SEP (1u << 11)
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#define bit_cpu_MTRR (1u << 12)
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#define bit_cpu_PGE (1u << 13)
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#define bit_cpu_MCA (1u << 14)
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#define bit_cpu_CMOV (1u << 15)
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#define bit_cpu_PAT (1u << 16)
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#define bit_cpu_PSE_36 (1u << 17)
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#define bit_cpu_PSN (1u << 18)
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#define bit_cpu_CLFSH (1u << 19)
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#define bit_cpu_INDEX_1_EDX_20 (1u << 20)
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#define bit_cpu_DS (1u << 21)
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#define bit_cpu_ACPI (1u << 22)
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#define bit_cpu_MMX (1u << 23)
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#define bit_cpu_FXSR (1u << 24)
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#define bit_cpu_SSE (1u << 25)
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#define bit_cpu_SSE2 (1u << 26)
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#define bit_cpu_SS (1u << 27)
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#define bit_cpu_HTT (1u << 28)
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#define bit_cpu_TM (1u << 29)
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#define bit_cpu_INDEX_1_EDX_30 (1u << 30)
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#define bit_cpu_PBE (1u << 31)
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/* COMMON_CPUID_INDEX_7. */
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/* EBX. */
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#define bit_cpu_FSGSBASE (1u << 0)
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#define bit_cpu_TSC_ADJUST (1u << 1)
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#define bit_cpu_SGX (1u << 2)
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#define bit_cpu_BMI1 (1u << 3)
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#define bit_cpu_HLE (1u << 4)
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#define bit_cpu_AVX2 (1u << 5)
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#define bit_cpu_INDEX_7_EBX_6 (1u << 6)
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#define bit_cpu_SMEP (1u << 7)
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#define bit_cpu_BMI2 (1u << 8)
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#define bit_cpu_ERMS (1u << 9)
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#define bit_cpu_INVPCID (1u << 10)
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#define bit_cpu_RTM (1u << 11)
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#define bit_cpu_RDT_M (1u << 12)
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#define bit_cpu_DEPR_FPU_CS_DS (1u << 13)
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#define bit_cpu_MPX (1u << 14)
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#define bit_cpu_RDT_A (1u << 15)
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#define bit_cpu_AVX512F (1u << 16)
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#define bit_cpu_AVX512DQ (1u << 17)
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#define bit_cpu_RDSEED (1u << 18)
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#define bit_cpu_ADX (1u << 19)
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#define bit_cpu_SMAP (1u << 20)
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#define bit_cpu_AVX512_IFMA (1u << 21)
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#define bit_cpu_INDEX_7_EBX_22 (1u << 22)
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#define bit_cpu_CLFLUSHOPT (1u << 23)
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#define bit_cpu_CLWB (1u << 24)
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#define bit_cpu_TRACE (1u << 25)
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#define bit_cpu_AVX512PF (1u << 26)
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#define bit_cpu_AVX512ER (1u << 27)
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#define bit_cpu_AVX512CD (1u << 28)
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#define bit_cpu_SHA (1u << 29)
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#define bit_cpu_AVX512BW (1u << 30)
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#define bit_cpu_AVX512VL (1u << 31)
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/* ECX. */
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#define bit_cpu_PREFETCHWT1 (1u << 0)
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#define bit_cpu_AVX512_VBMI (1u << 1)
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#define bit_cpu_UMIP (1u << 2)
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#define bit_cpu_PKU (1u << 3)
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#define bit_cpu_OSPKE (1u << 4)
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#define bit_cpu_WAITPKG (1u << 5)
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#define bit_cpu_AVX512_VBMI2 (1u << 6)
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#define bit_cpu_SHSTK (1u << 7)
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#define bit_cpu_GFNI (1u << 8)
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#define bit_cpu_VAES (1u << 9)
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#define bit_cpu_VPCLMULQDQ (1u << 10)
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#define bit_cpu_AVX512_VNNI (1u << 11)
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#define bit_cpu_AVX512_BITALG (1u << 12)
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#define bit_cpu_INDEX_7_ECX_13 (1u << 13)
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#define bit_cpu_AVX512_VPOPCNTDQ (1u << 14)
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#define bit_cpu_INDEX_7_ECX_15 (1u << 15)
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#define bit_cpu_INDEX_7_ECX_16 (1u << 16)
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/* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX
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instructions in 64-bit mode. */
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#define bit_cpu_RDPID (1u << 22)
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#define bit_cpu_KL (1u << 23)
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#define bit_cpu_INDEX_7_ECX_24 (1u << 24)
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#define bit_cpu_CLDEMOTE (1u << 25)
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#define bit_cpu_INDEX_7_ECX_26 (1u << 26)
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#define bit_cpu_MOVDIRI (1u << 27)
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#define bit_cpu_MOVDIR64B (1u << 28)
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#define bit_cpu_ENQCMD (1u << 29)
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#define bit_cpu_SGX_LC (1u << 30)
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#define bit_cpu_PKS (1u << 31)
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/* EDX. */
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#define bit_cpu_INDEX_7_EDX_0 (1u << 0)
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#define bit_cpu_INDEX_7_EDX_1 (1u << 1)
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#define bit_cpu_AVX512_4VNNIW (1u << 2)
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#define bit_cpu_AVX512_4FMAPS (1u << 3)
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#define bit_cpu_FSRM (1u << 4)
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#define bit_cpu_UINTR (1u << 5)
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#define bit_cpu_INDEX_7_EDX_6 (1u << 6)
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#define bit_cpu_INDEX_7_EDX_7 (1u << 7)
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#define bit_cpu_AVX512_VP2INTERSECT (1u << 8)
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#define bit_cpu_INDEX_7_EDX_9 (1u << 9)
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#define bit_cpu_MD_CLEAR (1u << 10)
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#define bit_cpu_INDEX_7_EDX_11 (1u << 11)
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#define bit_cpu_INDEX_7_EDX_12 (1u << 12)
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#define bit_cpu_INDEX_7_EDX_13 (1u << 13)
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#define bit_cpu_SERIALIZE (1u << 14)
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#define bit_cpu_HYBRID (1u << 15)
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#define bit_cpu_TSXLDTRK (1u << 16)
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#define bit_cpu_INDEX_7_EDX_17 (1u << 17)
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#define bit_cpu_PCONFIG (1u << 18)
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#define bit_cpu_INDEX_7_EDX_19 (1u << 19)
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#define bit_cpu_IBT (1u << 20)
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#define bit_cpu_INDEX_7_EDX_21 (1u << 21)
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#define bit_cpu_AMX_BF16 (1u << 22)
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#define bit_cpu_AVX512_FP16 (1u << 23)
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#define bit_cpu_AMX_TILE (1u << 24)
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#define bit_cpu_AMX_INT8 (1u << 25)
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#define bit_cpu_IBRS_IBPB (1u << 26)
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#define bit_cpu_STIBP (1u << 27)
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#define bit_cpu_L1D_FLUSH (1u << 28)
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#define bit_cpu_ARCH_CAPABILITIES (1u << 29)
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#define bit_cpu_CORE_CAPABILITIES (1u << 30)
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#define bit_cpu_SSBD (1u << 31)
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/* COMMON_CPUID_INDEX_80000001. */
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/* ECX. */
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#define bit_cpu_LAHF64_SAHF64 (1u << 0)
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#define bit_cpu_SVM (1u << 2)
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#define bit_cpu_LZCNT (1u << 5)
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#define bit_cpu_SSE4A (1u << 6)
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#define bit_cpu_PREFETCHW (1u << 8)
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#define bit_cpu_XOP (1u << 11)
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#define bit_cpu_LWP (1u << 15)
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#define bit_cpu_FMA4 (1u << 16)
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#define bit_cpu_TBM (1u << 21)
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/* EDX. */
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#define bit_cpu_SYSCALL_SYSRET (1u << 11)
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#define bit_cpu_NX (1u << 20)
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#define bit_cpu_PAGE1GB (1u << 26)
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#define bit_cpu_RDTSCP (1u << 27)
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#define bit_cpu_LM (1u << 29)
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/* COMMON_CPUID_INDEX_D_ECX_1. */
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/* EAX. */
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#define bit_cpu_XSAVEOPT (1u << 0)
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#define bit_cpu_XSAVEC (1u << 1)
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#define bit_cpu_XGETBV_ECX_1 (1u << 2)
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#define bit_cpu_XSAVES (1u << 3)
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#define bit_cpu_XFD (1u << 4)
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/* COMMON_CPUID_INDEX_80000007. */
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/* EDX. */
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#define bit_cpu_INVARIANT_TSC (1u << 8)
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/* COMMON_CPUID_INDEX_80000008. */
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/* EBX. */
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#define bit_cpu_WBNOINVD (1u << 9)
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/* COMMON_CPUID_INDEX_7_ECX_1. */
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/* EAX. */
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#define bit_cpu_AVX_VNNI (1u << 4)
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#define bit_cpu_AVX512_BF16 (1u << 5)
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#define bit_cpu_FZLRM (1u << 10)
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#define bit_cpu_FSRS (1u << 11)
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#define bit_cpu_FSRCS (1u << 12)
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#define bit_cpu_HRESET (1u << 22)
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#define bit_cpu_LAM (1u << 26)
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/* COMMON_CPUID_INDEX_19. */
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/* EBX. */
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#define bit_cpu_AESKLE (1u << 0)
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#define bit_cpu_WIDE_KL (1u << 2)
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/* COMMON_CPUID_INDEX_1. */
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/* ECX. */
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#define index_cpu_SSE3 COMMON_CPUID_INDEX_1
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#define index_cpu_PCLMULQDQ COMMON_CPUID_INDEX_1
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#define index_cpu_DTES64 COMMON_CPUID_INDEX_1
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#define index_cpu_MONITOR COMMON_CPUID_INDEX_1
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#define index_cpu_DS_CPL COMMON_CPUID_INDEX_1
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#define index_cpu_VMX COMMON_CPUID_INDEX_1
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#define index_cpu_SMX COMMON_CPUID_INDEX_1
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#define index_cpu_EIST COMMON_CPUID_INDEX_1
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#define index_cpu_TM2 COMMON_CPUID_INDEX_1
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#define index_cpu_SSSE3 COMMON_CPUID_INDEX_1
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#define index_cpu_CNXT_ID COMMON_CPUID_INDEX_1
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#define index_cpu_SDBG COMMON_CPUID_INDEX_1
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#define index_cpu_FMA COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_CMPXCHG16B COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_XTPRUPDCTRL COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_PDCM COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_INDEX_1_ECX_16 COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_PCID COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_DCA COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_SSE4_2 COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_X2APIC COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_MOVBE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_POPCNT COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_TSC_DEADLINE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_AES COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_XSAVE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_OSXSAVE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_AVX COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_F16C COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_RDRAND COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_INDEX_1_ECX_31 COMMON_CPUID_INDEX_1
|
||||
|
||||
/* ECX. */
|
||||
#define index_cpu_FPU COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_VME COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_DE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_PSE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_TSC COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_MSR COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_PAE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_MCE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_CX8 COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_APIC COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_INDEX_1_EDX_10 COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_SEP COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_MTRR COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_PGE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_MCA COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_CMOV COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_PAT COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_PSE_36 COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_PSN COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_CLFSH COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_INDEX_1_EDX_20 COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_DS COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_ACPI COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_MMX COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_FXSR COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_SSE COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_SSE2 COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_SS COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_HTT COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_TM COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_INDEX_1_EDX_30 COMMON_CPUID_INDEX_1
|
||||
#define index_cpu_PBE COMMON_CPUID_INDEX_1
|
||||
|
||||
/* COMMON_CPUID_INDEX_7. */
|
||||
|
||||
/* EBX. */
|
||||
#define index_cpu_FSGSBASE COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_TSC_ADJUST COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_SGX COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_BMI1 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_HLE COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX2 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EBX_6 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_SMEP COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_BMI2 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_ERMS COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INVPCID COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_RTM COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_RDT_M COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_DEPR_FPU_CS_DS COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_MPX COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_RDT_A COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512F COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512DQ COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_RDSEED COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_ADX COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_SMAP COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_IFMA COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EBX_22 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_CLFLUSHOPT COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_CLWB COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_TRACE COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512PF COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512ER COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512CD COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_SHA COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512BW COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512VL COMMON_CPUID_INDEX_7
|
||||
|
||||
/* ECX. */
|
||||
#define index_cpu_PREFETCHWT1 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_VBMI COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_UMIP COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_PKU COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_OSPKE COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_WAITPKG COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_VBMI2 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_SHSTK COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_GFNI COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_VAES COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_VPCLMULQDQ COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_VNNI COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_BITALG COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_ECX_13 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_VPOPCNTDQ COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_ECX_15 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_ECX_16 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_RDPID COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_KL COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_ECX_24 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_CLDEMOTE COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_ECX_26 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_MOVDIRI COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_MOVDIR64B COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_ENQCMD COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_SGX_LC COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_PKS COMMON_CPUID_INDEX_7
|
||||
|
||||
/* EDX. */
|
||||
#define index_cpu_INDEX_7_EDX_0 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_1 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_4VNNIW COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_4FMAPS COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_FSRM COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_UINTR COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_6 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_7 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_VP2INTERSECT COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_9 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_MD_CLEAR COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_11 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_12 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_13 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_SERIALIZE COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_HYBRID COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_TSXLDTRK COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_17 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_PCONFIG COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_19 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_IBT COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_INDEX_7_EDX_21 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AMX_BF16 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AVX512_FP16 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AMX_TILE COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_AMX_INT8 COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_IBRS_IBPB COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_STIBP COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_L1D_FLUSH COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_ARCH_CAPABILITIES COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_CORE_CAPABILITIES COMMON_CPUID_INDEX_7
|
||||
#define index_cpu_SSBD COMMON_CPUID_INDEX_7
|
||||
|
||||
/* COMMON_CPUID_INDEX_80000001. */
|
||||
|
||||
/* ECX. */
|
||||
#define index_cpu_LAHF64_SAHF64 COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_SVM COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_LZCNT COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_SSE4A COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_PREFETCHW COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_XOP COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_LWP COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_FMA4 COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_TBM COMMON_CPUID_INDEX_80000001
|
||||
|
||||
/* EDX. */
|
||||
#define index_cpu_SYSCALL_SYSRET COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_NX COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_PAGE1GB COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_RDTSCP COMMON_CPUID_INDEX_80000001
|
||||
#define index_cpu_LM COMMON_CPUID_INDEX_80000001
|
||||
|
||||
/* COMMON_CPUID_INDEX_D_ECX_1. */
|
||||
|
||||
/* EAX. */
|
||||
#define index_cpu_XSAVEOPT COMMON_CPUID_INDEX_D_ECX_1
|
||||
#define index_cpu_XSAVEC COMMON_CPUID_INDEX_D_ECX_1
|
||||
#define index_cpu_XGETBV_ECX_1 COMMON_CPUID_INDEX_D_ECX_1
|
||||
#define index_cpu_XSAVES COMMON_CPUID_INDEX_D_ECX_1
|
||||
#define index_cpu_XFD COMMON_CPUID_INDEX_D_ECX_1
|
||||
|
||||
/* COMMON_CPUID_INDEX_80000007. */
|
||||
|
||||
/* EDX. */
|
||||
#define index_cpu_INVARIANT_TSC COMMON_CPUID_INDEX_80000007
|
||||
|
||||
/* COMMON_CPUID_INDEX_80000008. */
|
||||
|
||||
/* EBX. */
|
||||
#define index_cpu_WBNOINVD COMMON_CPUID_INDEX_80000008
|
||||
|
||||
/* COMMON_CPUID_INDEX_7_ECX_1. */
|
||||
|
||||
/* EAX. */
|
||||
#define index_cpu_AVX_VNNI COMMON_CPUID_INDEX_7_ECX_1
|
||||
#define index_cpu_AVX512_BF16 COMMON_CPUID_INDEX_7_ECX_1
|
||||
#define index_cpu_FZLRM COMMON_CPUID_INDEX_7_ECX_1
|
||||
#define index_cpu_FSRS COMMON_CPUID_INDEX_7_ECX_1
|
||||
#define index_cpu_FSRCS COMMON_CPUID_INDEX_7_ECX_1
|
||||
#define index_cpu_HRESET COMMON_CPUID_INDEX_7_ECX_1
|
||||
#define index_cpu_LAM COMMON_CPUID_INDEX_7_ECX_1
|
||||
|
||||
/* COMMON_CPUID_INDEX_19. */
|
||||
|
||||
/* EBX. */
|
||||
#define index_cpu_AESKLE COMMON_CPUID_INDEX_19
|
||||
#define index_cpu_WIDE_KL COMMON_CPUID_INDEX_19
|
||||
|
||||
/* COMMON_CPUID_INDEX_1. */
|
||||
|
||||
/* ECX. */
|
||||
#define reg_SSE3 ecx
|
||||
#define reg_PCLMULQDQ ecx
|
||||
#define reg_DTES64 ecx
|
||||
#define reg_MONITOR ecx
|
||||
#define reg_DS_CPL ecx
|
||||
#define reg_VMX ecx
|
||||
#define reg_SMX ecx
|
||||
#define reg_EIST ecx
|
||||
#define reg_TM2 ecx
|
||||
#define reg_SSSE3 ecx
|
||||
#define reg_CNXT_ID ecx
|
||||
#define reg_SDBG ecx
|
||||
#define reg_FMA ecx
|
||||
#define reg_CMPXCHG16B ecx
|
||||
#define reg_XTPRUPDCTRL ecx
|
||||
#define reg_PDCM ecx
|
||||
#define reg_INDEX_1_ECX_16 ecx
|
||||
#define reg_PCID ecx
|
||||
#define reg_DCA ecx
|
||||
#define reg_SSE4_1 ecx
|
||||
#define reg_SSE4_2 ecx
|
||||
#define reg_X2APIC ecx
|
||||
#define reg_MOVBE ecx
|
||||
#define reg_POPCNT ecx
|
||||
#define reg_TSC_DEADLINE ecx
|
||||
#define reg_AES ecx
|
||||
#define reg_XSAVE ecx
|
||||
#define reg_OSXSAVE ecx
|
||||
#define reg_AVX ecx
|
||||
#define reg_F16C ecx
|
||||
#define reg_RDRAND ecx
|
||||
#define reg_INDEX_1_ECX_31 ecx
|
||||
|
||||
/* EDX. */
|
||||
#define reg_FPU edx
|
||||
#define reg_VME edx
|
||||
#define reg_DE edx
|
||||
#define reg_PSE edx
|
||||
#define reg_TSC edx
|
||||
#define reg_MSR edx
|
||||
#define reg_PAE edx
|
||||
#define reg_MCE edx
|
||||
#define reg_CX8 edx
|
||||
#define reg_APIC edx
|
||||
#define reg_INDEX_1_EDX_10 edx
|
||||
#define reg_SEP edx
|
||||
#define reg_MTRR edx
|
||||
#define reg_PGE edx
|
||||
#define reg_MCA edx
|
||||
#define reg_CMOV edx
|
||||
#define reg_PAT edx
|
||||
#define reg_PSE_36 edx
|
||||
#define reg_PSN edx
|
||||
#define reg_CLFSH edx
|
||||
#define reg_INDEX_1_EDX_20 edx
|
||||
#define reg_DS edx
|
||||
#define reg_ACPI edx
|
||||
#define reg_MMX edx
|
||||
#define reg_FXSR edx
|
||||
#define reg_SSE edx
|
||||
#define reg_SSE2 edx
|
||||
#define reg_SS edx
|
||||
#define reg_HTT edx
|
||||
#define reg_TM edx
|
||||
#define reg_INDEX_1_EDX_30 edx
|
||||
#define reg_PBE edx
|
||||
|
||||
/* COMMON_CPUID_INDEX_7. */
|
||||
|
||||
/* EBX. */
|
||||
#define reg_FSGSBASE ebx
|
||||
#define reg_TSC_ADJUST ebx
|
||||
#define reg_SGX ebx
|
||||
#define reg_BMI1 ebx
|
||||
#define reg_HLE ebx
|
||||
#define reg_BMI2 ebx
|
||||
#define reg_AVX2 ebx
|
||||
#define reg_INDEX_7_EBX_6 ebx
|
||||
#define reg_SMEP ebx
|
||||
#define reg_ERMS ebx
|
||||
#define reg_INVPCID ebx
|
||||
#define reg_RTM ebx
|
||||
#define reg_RDT_M ebx
|
||||
#define reg_DEPR_FPU_CS_DS ebx
|
||||
#define reg_MPX ebx
|
||||
#define reg_RDT_A ebx
|
||||
#define reg_AVX512F ebx
|
||||
#define reg_AVX512DQ ebx
|
||||
#define reg_RDSEED ebx
|
||||
#define reg_ADX ebx
|
||||
#define reg_SMAP ebx
|
||||
#define reg_AVX512_IFMA ebx
|
||||
#define reg_INDEX_7_EBX_22 ebx
|
||||
#define reg_CLFLUSHOPT ebx
|
||||
#define reg_CLWB ebx
|
||||
#define reg_TRACE ebx
|
||||
#define reg_AVX512PF ebx
|
||||
#define reg_AVX512ER ebx
|
||||
#define reg_AVX512CD ebx
|
||||
#define reg_SHA ebx
|
||||
#define reg_AVX512BW ebx
|
||||
#define reg_AVX512VL ebx
|
||||
|
||||
/* ECX. */
|
||||
#define reg_PREFETCHWT1 ecx
|
||||
#define reg_AVX512_VBMI ecx
|
||||
#define reg_UMIP ecx
|
||||
#define reg_PKU ecx
|
||||
#define reg_OSPKE ecx
|
||||
#define reg_WAITPKG ecx
|
||||
#define reg_AVX512_VBMI2 ecx
|
||||
#define reg_SHSTK ecx
|
||||
#define reg_GFNI ecx
|
||||
#define reg_VAES ecx
|
||||
#define reg_VPCLMULQDQ ecx
|
||||
#define reg_AVX512_VNNI ecx
|
||||
#define reg_AVX512_BITALG ecx
|
||||
#define reg_INDEX_7_ECX_13 ecx
|
||||
#define reg_AVX512_VPOPCNTDQ ecx
|
||||
#define reg_INDEX_7_ECX_15 ecx
|
||||
#define reg_INDEX_7_ECX_16 ecx
|
||||
#define reg_RDPID ecx
|
||||
#define reg_KL ecx
|
||||
#define reg_INDEX_7_ECX_24 ecx
|
||||
#define reg_CLDEMOTE ecx
|
||||
#define reg_INDEX_7_ECX_26 ecx
|
||||
#define reg_MOVDIRI ecx
|
||||
#define reg_MOVDIR64B ecx
|
||||
#define reg_ENQCMD ecx
|
||||
#define reg_SGX_LC ecx
|
||||
#define reg_PKS ecx
|
||||
|
||||
/* EDX. */
|
||||
#define reg_INDEX_7_EDX_0 edx
|
||||
#define reg_INDEX_7_EDX_1 edx
|
||||
#define reg_AVX512_4VNNIW edx
|
||||
#define reg_AVX512_4FMAPS edx
|
||||
#define reg_FSRM edx
|
||||
#define reg_UINTR edx
|
||||
#define reg_INDEX_7_EDX_6 edx
|
||||
#define reg_INDEX_7_EDX_7 edx
|
||||
#define reg_AVX512_VP2INTERSECT edx
|
||||
#define reg_INDEX_7_EDX_9 edx
|
||||
#define reg_MD_CLEAR edx
|
||||
#define reg_INDEX_7_EDX_11 edx
|
||||
#define reg_INDEX_7_EDX_12 edx
|
||||
#define reg_INDEX_7_EDX_13 edx
|
||||
#define reg_SERIALIZE edx
|
||||
#define reg_HYBRID edx
|
||||
#define reg_TSXLDTRK edx
|
||||
#define reg_INDEX_7_EDX_17 edx
|
||||
#define reg_PCONFIG edx
|
||||
#define reg_INDEX_7_EDX_19 edx
|
||||
#define reg_IBT edx
|
||||
#define reg_INDEX_7_EDX_21 edx
|
||||
#define reg_AMX_BF16 edx
|
||||
#define reg_AVX512_FP16 edx
|
||||
#define reg_AMX_TILE edx
|
||||
#define reg_AMX_INT8 edx
|
||||
#define reg_IBRS_IBPB edx
|
||||
#define reg_STIBP edx
|
||||
#define reg_L1D_FLUSH edx
|
||||
#define reg_ARCH_CAPABILITIES edx
|
||||
#define reg_CORE_CAPABILITIES edx
|
||||
#define reg_SSBD edx
|
||||
|
||||
/* COMMON_CPUID_INDEX_80000001. */
|
||||
|
||||
/* ECX. */
|
||||
#define reg_LAHF64_SAHF64 ecx
|
||||
#define reg_SVM ecx
|
||||
#define reg_LZCNT ecx
|
||||
#define reg_SSE4A ecx
|
||||
#define reg_PREFETCHW ecx
|
||||
#define reg_XOP ecx
|
||||
#define reg_LWP ecx
|
||||
#define reg_FMA4 ecx
|
||||
#define reg_TBM ecx
|
||||
|
||||
/* EDX. */
|
||||
#define reg_SYSCALL_SYSRET edx
|
||||
#define reg_NX edx
|
||||
#define reg_PAGE1GB edx
|
||||
#define reg_RDTSCP edx
|
||||
#define reg_LM edx
|
||||
|
||||
/* COMMON_CPUID_INDEX_D_ECX_1. */
|
||||
|
||||
/* EAX. */
|
||||
#define reg_XSAVEOPT eax
|
||||
#define reg_XSAVEC eax
|
||||
#define reg_XGETBV_ECX_1 eax
|
||||
#define reg_XSAVES eax
|
||||
#define reg_XFD eax
|
||||
|
||||
/* COMMON_CPUID_INDEX_80000007. */
|
||||
|
||||
/* EDX. */
|
||||
#define reg_INVARIANT_TSC edx
|
||||
|
||||
/* COMMON_CPUID_INDEX_80000008. */
|
||||
|
||||
/* EBX. */
|
||||
#define reg_WBNOINVD ebx
|
||||
|
||||
/* COMMON_CPUID_INDEX_7_ECX_1. */
|
||||
|
||||
/* EAX. */
|
||||
#define reg_AVX_VNNI eax
|
||||
#define reg_AVX512_BF16 eax
|
||||
#define reg_FZLRM eax
|
||||
#define reg_FSRS eax
|
||||
#define reg_FSRCS eax
|
||||
#define reg_HRESET eax
|
||||
#define reg_LAM eax
|
||||
|
||||
/* COMMON_CPUID_INDEX_19. */
|
||||
|
||||
/* EBX. */
|
||||
#define reg_AESKLE ebx
|
||||
#define reg_WIDE_KL ebx
|
||||
__END_DECLS
|
||||
|
||||
#endif /* _SYS_PLATFORM_X86_H */
|
||||
|
||||
Reference in New Issue
Block a user