1
0
mirror of https://sourceware.org/git/glibc.git synced 2025-08-01 10:06:57 +03:00

Use __glibc_reserved convention in mcontext, sigcontext (bug 21457).

This patch implements the most straightforward part of fixing
namespace issues for sys/ucontext.h and related headers: where fields
in sys/ucontext.h or bits/sigcontext.h are named "reserved", "padding"
or similar, they are renamed to use the __glibc_reserved* naming
convention.  It does not change fields with a leading underscore, or
even those with a prefix such as uc_ or sc_.  It only fixes a small
part of bug 21457, so no XFAILs are removed.

Tested for x86_64 and x86, and with build-many-glibcs.py.

	[BZ #21457]
	* sysdeps/unix/sysv/linux/mips/sys/ucontext.h
	[_MIPS_SIM != _ABIO32] (mcontext_t): Rename field reserved to
	__glibc_reserved1.
	* sysdeps/unix/sysv/linux/x86/bits/sigcontext.h
	(struct _fpx_sw_bytes): Rename field padding to __glibc_reserved1.
	(struct _fpxreg): Likewise.
	[!__x86_64__] (struct _fpstate): Rename field reserved to
	__glibc_reserved1.  Rename field padding to __glibc_reserved2.
	[__x86_64__] (struct _fpstate): Rename field padding to
	__glibc_reserved1.
	(struct _xsave_hdr): Rename field reserved1 to __glibc_reserved1.
	Rename field reserved2 to __glibc_reserved2.
	* sysdeps/unix/sysv/linux/x86/sys/ucontext.h
	[__x86_64__] (struct _libc_fpxreg): Rename field padding to
	__glibc_reserved1.
	[__x86_64__] (struct _libc_fpstate): Rename field padding to
	__glibc_reserved1.
This commit is contained in:
Joseph Myers
2017-05-04 11:26:33 +00:00
parent 808befbf9e
commit fd9f30f6f9
4 changed files with 31 additions and 10 deletions

View File

@ -95,7 +95,7 @@ struct _libc_fpxreg
{
unsigned short int significand[4];
unsigned short int exponent;
unsigned short int padding[3];
unsigned short int __glibc_reserved1[3];
};
struct _libc_xmmreg
@ -116,7 +116,7 @@ struct _libc_fpstate
__uint32_t mxcr_mask;
struct _libc_fpxreg _st[8];
struct _libc_xmmreg _xmm[16];
__uint32_t padding[24];
__uint32_t __glibc_reserved1[24];
};
/* Structure to describe FPU registers. */