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x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444]

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commit 2d651eb926
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Fri Sep 18 07:55:14 2020 -0700

    x86: Move x86 processor cache info to cpu_features

missed _SC_LEVEL1_ICACHE_LINESIZE.

1. Add level1_icache_linesize to struct cpu_features.
2. Initialize level1_icache_linesize by calling handle_intel,
handle_zhaoxin and handle_amd with _SC_LEVEL1_ICACHE_LINESIZE.
3. Return level1_icache_linesize for _SC_LEVEL1_ICACHE_LINESIZE.

Reviewed-by: Carlos O'Donell <carlos@redhat.com>
This commit is contained in:
H.J. Lu
2021-03-06 10:19:32 -08:00
parent 3324213125
commit f53ffc9b90
7 changed files with 79 additions and 0 deletions
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sysdeps/x86/tst-sysconf-cache-linesize-static.c Normal file
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#include "tst-sysconf-cache-linesize.c"