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Avoid performance penalty in sparc optimized memcpy/memset.

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fmovd clears the current exception field in the %fsr, fsrc2
does not and therefore runs more efficiently on some cpus.

	* sysdeps/sparc/sparc64/memcpy.S: Use fsrc2 to move 64-bit
	values between float registers.
	* sysdeps/sparc/sparc64/memset.S: Likewise.
	* sysdeps/sparc/sparc64/multiarch/memcpy-niagara2.S: Likewise.
This commit is contained in:
David S. Miller
2012-05-31 14:19:30 -07:00
parent fed806c3af
commit f230c29b40
4 changed files with 54 additions and 47 deletions
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72
sysdeps/sparc/sparc64/multiarch/memcpy-niagara2.S
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@ -58,49 +58,49 @@
faligndata %x7, %x8, %f14;
#define FREG_MOVE_1(x0) \
fmovd %x0, %f0;
fsrc2 %x0, %f0;
#define FREG_MOVE_2(x0, x1) \
fmovd %x0, %f0; \
fmovd %x1, %f2;
fsrc2 %x0, %f0; \
fsrc2 %x1, %f2;
#define FREG_MOVE_3(x0, x1, x2) \
fmovd %x0, %f0; \
fmovd %x1, %f2; \
fmovd %x2, %f4;
fsrc2 %x0, %f0; \
fsrc2 %x1, %f2; \
fsrc2 %x2, %f4;
#define FREG_MOVE_4(x0, x1, x2, x3) \
fmovd %x0, %f0; \
fmovd %x1, %f2; \
fmovd %x2, %f4; \
fmovd %x3, %f6;
fsrc2 %x0, %f0; \
fsrc2 %x1, %f2; \
fsrc2 %x2, %f4; \
fsrc2 %x3, %f6;
#define FREG_MOVE_5(x0, x1, x2, x3, x4) \
fmovd %x0, %f0; \
fmovd %x1, %f2; \
fmovd %x2, %f4; \
fmovd %x3, %f6; \
fmovd %x4, %f8;
fsrc2 %x0, %f0; \
fsrc2 %x1, %f2; \
fsrc2 %x2, %f4; \
fsrc2 %x3, %f6; \
fsrc2 %x4, %f8;
#define FREG_MOVE_6(x0, x1, x2, x3, x4, x5) \
fmovd %x0, %f0; \
fmovd %x1, %f2; \
fmovd %x2, %f4; \
fmovd %x3, %f6; \
fmovd %x4, %f8; \
fmovd %x5, %f10;
fsrc2 %x0, %f0; \
fsrc2 %x1, %f2; \
fsrc2 %x2, %f4; \
fsrc2 %x3, %f6; \
fsrc2 %x4, %f8; \
fsrc2 %x5, %f10;
#define FREG_MOVE_7(x0, x1, x2, x3, x4, x5, x6) \
fmovd %x0, %f0; \
fmovd %x1, %f2; \
fmovd %x2, %f4; \
fmovd %x3, %f6; \
fmovd %x4, %f8; \
fmovd %x5, %f10; \
fmovd %x6, %f12;
fsrc2 %x0, %f0; \
fsrc2 %x1, %f2; \
fsrc2 %x2, %f4; \
fsrc2 %x3, %f6; \
fsrc2 %x4, %f8; \
fsrc2 %x5, %f10; \
fsrc2 %x6, %f12;
#define FREG_MOVE_8(x0, x1, x2, x3, x4, x5, x6, x7) \
fmovd %x0, %f0; \
fmovd %x1, %f2; \
fmovd %x2, %f4; \
fmovd %x3, %f6; \
fmovd %x4, %f8; \
fmovd %x5, %f10; \
fmovd %x6, %f12; \
fmovd %x7, %f14;
fsrc2 %x0, %f0; \
fsrc2 %x1, %f2; \
fsrc2 %x2, %f4; \
fsrc2 %x3, %f6; \
fsrc2 %x4, %f8; \
fsrc2 %x5, %f10; \
fsrc2 %x6, %f12; \
fsrc2 %x7, %f14;
#define FREG_LOAD_1(base, x0) \
LOAD(ldd, base + 0x00, %x0)
#define FREG_LOAD_2(base, x0, x1) \