mirror of
https://sourceware.org/git/glibc.git
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[BZ #6411]
2008-11-13 Ryan S. Arnold <rsa@us.ibm.com> [BZ #6411] * sysdeps/powerpc/fpu/Makefile: Added test case tst-setcontext-fpscr. * sysdeps/powerpc/fpu/feholdexcpt.c (_FPU_MASK_ALL): Define to replace magic numbers. * sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_register): Dynamically choose mtfsf insn based on PPC_FEATURE_HAS_DFP. (relax_fenv_state): Same as above. (FPSCR_29): Reserve bit in ISA 2.05. (FPSCR_NI): Provide define for compat. * sysdeps/powerpc/fpu/fesetenv.c (_FPU_MASK_ALL): Define to replace magic numbers. * sysdeps/powerpc/fpu/feupdateenv.c (_FPU_MASK_ALL): Define to replace magic numbers. * sysdeps/powerpc/fpu/tst-setcontext-fpscr.c: New file. Test case to test setcontext and swapcontext with dynamic 64-bit FPSCR detection. * sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S (__longjmp): Adjust access to hwcap to account for hwcap size increase to uint64_t. * sysdeps/powerpc/powerpc32/fpu/setjmp-common.S (__sigsetjmp ): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S (*setcontext): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S (*setcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP. Adjust access to hwcap to account for hwcap size increase to uint64_t. * sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S (*swapcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP. Adjust access to hwcap to account for hwcap size increase to uint64_t. * sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S (*setcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP. * sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S (*swapcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP.
This commit is contained in:
Ulrich Drepper
@ -157,15 +157,15 @@ ENTRY(__CONTEXT_FUNC_NAME)
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# ifdef SHARED
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lwz r7,_rtld_global_ro@got(r7)
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mtlr r8
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
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# else
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lwz r7,_dl_hwcap@got(r7)
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mtlr r8
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lwz r7,0(r7)
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lwz r7,4(r7)
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# endif
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# else
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lis r7,_dl_hwcap@ha
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lwz r7,_dl_hwcap@l(r7)
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lis r7,(_dl_hwcap+4)@ha
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lwz r7,(_dl_hwcap+4)@l(r7)
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# endif
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andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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@ -0,0 +1,2 @@
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#define _ARCH_PWR6
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#include_next <setcontext.S>
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@ -0,0 +1,2 @@
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#define _ARCH_PWR6
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#include_next <swapcontext.S>
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@ -1,5 +1,5 @@
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/* Jump to a new context powerpc32 common.
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Copyright (C) 2005, 2006 Free Software Foundation, Inc.
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Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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@ -71,33 +71,34 @@ ENTRY(__CONTEXT_FUNC_NAME)
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cmpwi r3,0
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bne 3f /* L(error_exit) */
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#ifdef __CONTEXT_ENABLE_FPRS
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# ifdef __CONTEXT_ENABLE_VRS
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# ifdef PIC
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#ifdef PIC
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mflr r8
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# ifdef HAVE_ASM_PPC_REL16
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# ifdef HAVE_ASM_PPC_REL16
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bcl 20,31,1f
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1: mflr r7
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addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
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addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
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# else
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# else
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bl _GLOBAL_OFFSET_TABLE_@local-4
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mflr r7
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# endif
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# ifdef SHARED
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# endif
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# ifdef SHARED
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lwz r7,_rtld_global_ro@got(r7)
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mtlr r8
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
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# else
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
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# else
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lwz r7,_dl_hwcap@got(r7)
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mtlr r8
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lwz r7,0(r7)
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# endif
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# else
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lis r7,_dl_hwcap@ha
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lwz r7,_dl_hwcap@l(r7)
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# endif
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andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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lwz r7,4(r7)
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# endif
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#else
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lis r7,(_dl_hwcap+4)@ha
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lwz r7,(_dl_hwcap+4)@l(r7)
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#endif
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#ifdef __CONTEXT_ENABLE_FPRS
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# ifdef __CONTEXT_ENABLE_VRS
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andis. r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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la r10,(_UC_VREGS)(r31)
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beq 2f /* L(has_no_vec) */
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@ -199,7 +200,20 @@ ENTRY(__CONTEXT_FUNC_NAME)
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/* Restore the floating-point registers */
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lfd fp31,_UC_FREGS+(32*8)(r31)
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lfd fp0,_UC_FREGS+(0*8)(r31)
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mtfsf 0xff,fp31
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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# else
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r7,PPC_FEATURE_HAS_DFP
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beq 7f
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp31,1,0
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b 8f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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7: mtfsf 0xff,fp31
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8:
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# endif /* _ARCH_PWR6 */
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lfd fp1,_UC_FREGS+(1*8)(r31)
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lfd fp2,_UC_FREGS+(2*8)(r31)
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lfd fp3,_UC_FREGS+(3*8)(r31)
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@ -1,5 +1,5 @@
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/* Save current context and jump to a new context.
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Copyright (C) 2005, 2006 Free Software Foundation, Inc.
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Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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@ -143,33 +143,34 @@ ENTRY(__CONTEXT_FUNC_NAME)
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stfd fp30,_UC_FREGS+(30*8)(r3)
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stfd fp31,_UC_FREGS+(31*8)(r3)
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stfd fp0,_UC_FREGS+(32*8)(r3)
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# ifdef __CONTEXT_ENABLE_VRS
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# ifdef PIC
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# ifdef PIC
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mflr r8
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# ifdef HAVE_ASM_PPC_REL16
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# ifdef HAVE_ASM_PPC_REL16
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bcl 20,31,1f
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1: mflr r7
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addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
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addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
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# else
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# else
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bl _GLOBAL_OFFSET_TABLE_@local-4
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mflr r7
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# endif
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# ifdef SHARED
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# endif
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# ifdef SHARED
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lwz r7,_rtld_global_ro@got(r7)
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mtlr r8
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
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# else
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
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# else
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lwz r7,_dl_hwcap@got(r7)
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mtlr r8
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lwz r7,0(r7)
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# endif
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# else
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lis r7,_dl_hwcap@ha
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lwz r7,_dl_hwcap@l(r7)
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lwz r7,4(r7)
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# endif
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andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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# else
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lis r7,(_dl_hwcap+4)@ha
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lwz r7,(_dl_hwcap+4)@l(r7)
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# endif
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# ifdef __CONTEXT_ENABLE_VRS
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andis. r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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la r10,(_UC_VREGS)(r3)
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la r9,(_UC_VREGS+16)(r3)
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@ -305,8 +306,8 @@ ENTRY(__CONTEXT_FUNC_NAME)
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# ifdef HAVE_ASM_PPC_REL16
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bcl 20,31,5f
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5: mflr r7
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addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
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addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
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addis r7,r7,_GLOBAL_OFFSET_TABLE_-5b@ha
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addi r7,r7,_GLOBAL_OFFSET_TABLE_-5b@l
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# else
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bl _GLOBAL_OFFSET_TABLE_@local-4
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mflr r7
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@ -314,14 +315,14 @@ ENTRY(__CONTEXT_FUNC_NAME)
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mtlr r8
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# ifdef SHARED
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lwz r7,_rtld_global_ro@got(r7)
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
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lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
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# else
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lwz r7,_dl_hwcap@got(r7)
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lwz r7,0(r7)
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lwz r7,4(r7)
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# endif
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# else
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lis r7,_dl_hwcap@ha
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lwz r7,_dl_hwcap@l(r7)
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lis r7,(_dl_hwcap+4)@ha
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lwz r7,(_dl_hwcap+4)@l(r7)
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# endif
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andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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la r10,(_UC_VREGS)(r31)
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@ -425,7 +426,20 @@ ENTRY(__CONTEXT_FUNC_NAME)
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/* Restore the floating-point registers */
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lfd fp31,_UC_FREGS+(32*8)(r31)
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lfd fp0,_UC_FREGS+(0*8)(r31)
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mtfsf 0xff,fp31
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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# else
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r7,PPC_FEATURE_HAS_DFP
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beq 7f
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp31,1,0
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b 8f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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7: mtfsf 0xff,fp31
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8:
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#endif /* _ARCH_PWR6 */
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lfd fp1,_UC_FREGS+(1*8)(r31)
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lfd fp2,_UC_FREGS+(2*8)(r31)
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lfd fp3,_UC_FREGS+(3*8)(r31)
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@ -0,0 +1,2 @@
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#define _ARCH_PWR6
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#include_next <setcontext.S>
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@ -0,0 +1,2 @@
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#define _ARCH_PWR6
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#include_next <swapcontext.S>
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@ -1,5 +1,5 @@
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/* Switch to context.
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Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
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Copyright (C) 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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@ -27,6 +27,15 @@
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#include "ucontext_i.h"
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#include <asm/errno.h>
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.section ".toc","aw"
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.LC__dl_hwcap:
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#ifdef SHARED
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.tc _rtld_global_ro[TC],_rtld_global_ro
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#else
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.tc _dl_hwcap[TC],_dl_hwcap
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#endif
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.section ".text"
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#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
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ENTRY(__novec_setcontext)
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CALL_MCOUNT 1
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@ -62,10 +71,32 @@ ENTRY(__novec_setcontext)
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cmpdi r3,0
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bne L(nv_error_exit)
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# ifdef SHARED
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/* Load _rtld-global._dl_hwcap. */
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ld r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
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# else
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ld r5,0(r5) /* Load extern _dl_hwcap. */
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# endif
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lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
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lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
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lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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# else
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r5,PPC_FEATURE_HAS_DFP
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beq 5f
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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b 6f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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5:
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mtfsf 0xff,fp0
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6:
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# endif /* _ARCH_PWR6 */
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lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
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lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
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lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
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@ -189,15 +220,7 @@ compat_symbol (libc, __novec_setcontext, setcontext, GLIBC_2_3)
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#endif
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.section ".toc","aw"
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.LC__dl_hwcap:
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#ifdef SHARED
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.tc _rtld_global_ro[TC],_rtld_global_ro
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#else
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.tc _dl_hwcap[TC],_dl_hwcap
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#endif
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.section ".text"
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.machine "altivec"
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ENTRY(__setcontext)
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CALL_MCOUNT 1
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@ -241,7 +264,7 @@ ENTRY(__setcontext)
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# else
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ld r5,0(r5) /* Load extern _dl_hwcap. */
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# endif
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andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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andis. r6,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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beq L(has_no_vec)
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cmpdi r10,0
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@ -346,7 +369,22 @@ L(has_no_vec):
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lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
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lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
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lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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# else
|
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r5,PPC_FEATURE_HAS_DFP
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beq 7f
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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b 8f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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7:
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mtfsf 0xff,fp0
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8:
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# endif /* _ARCH_PWR6 */
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lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
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lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
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lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
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|
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@ -1,5 +1,5 @@
|
||||
/* Save current context and install the given one.
|
||||
Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
|
||||
Copyright (C) 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
|
||||
This file is part of the GNU C Library.
|
||||
|
||||
The GNU C Library is free software; you can redistribute it and/or
|
||||
@ -27,7 +27,16 @@
|
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#include "ucontext_i.h"
|
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#include <asm/errno.h>
|
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|
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.section ".toc","aw"
|
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.LC__dl_hwcap:
|
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#ifdef SHARED
|
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.tc _rtld_global_ro[TC],_rtld_global_ro
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#else
|
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.tc _dl_hwcap[TC],_dl_hwcap
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#endif
|
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|
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#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
|
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.section ".text"
|
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ENTRY(__novec_swapcontext)
|
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CALL_MCOUNT 2
|
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#ifdef __ASSUME_NEW_RT_SIGRETURN_SYSCALL
|
||||
@ -157,10 +166,31 @@ ENTRY(__novec_swapcontext)
|
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cmpdi r0,0
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bne L(nv_do_sigret)
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|
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# ifdef SHARED
|
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/* Load _rtld-global._dl_hwcap. */
|
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ld r8,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r8)
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# else
|
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ld r8,0(r8) /* Load extern _dl_hwcap. */
|
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# endif
|
||||
|
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lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
|
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lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
|
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lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
|
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# ifdef _ARCH_PWR6
|
||||
/* Use the extended four-operand version of the mtfsf insn. */
|
||||
mtfsf 0xff,fp0,1,0
|
||||
# else
|
||||
/* Availability of DFP indicates a 64-bit FPSCR. */
|
||||
andi. r6,r8,PPC_FEATURE_HAS_DFP
|
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beq 5f
|
||||
/* Use the extended four-operand version of the mtfsf insn. */
|
||||
mtfsf 0xff,fp0,1,0
|
||||
b 6f
|
||||
/* Continue to operate on the FPSCR as if it were 32-bits. */
|
||||
5:
|
||||
mtfsf 0xff,fp0
|
||||
6:
|
||||
#endif /* _ARCH_PWR6 */
|
||||
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
|
||||
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
|
||||
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
|
||||
@ -283,15 +313,7 @@ compat_symbol (libc, __novec_swapcontext, swapcontext, GLIBC_2_3)
|
||||
|
||||
#endif
|
||||
|
||||
.section ".toc","aw"
|
||||
.LC__dl_hwcap:
|
||||
#ifdef SHARED
|
||||
.tc _rtld_global_ro[TC],_rtld_global_ro
|
||||
#else
|
||||
.tc _dl_hwcap[TC],_dl_hwcap
|
||||
#endif
|
||||
.section ".text"
|
||||
|
||||
.machine "altivec"
|
||||
ENTRY(__swapcontext)
|
||||
CALL_MCOUNT 2
|
||||
@ -409,7 +431,7 @@ ENTRY(__swapcontext)
|
||||
la r10,(SIGCONTEXT_V_RESERVE+8)(r3)
|
||||
la r9,(SIGCONTEXT_V_RESERVE+24)(r3)
|
||||
|
||||
andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
|
||||
andis. r6,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
|
||||
|
||||
clrrdi r10,r10,4
|
||||
beq L(has_no_vec)
|
||||
@ -540,7 +562,7 @@ L(has_no_vec):
|
||||
# else
|
||||
ld r8,0(r8) /* Load extern _dl_hwcap. */
|
||||
# endif
|
||||
andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
|
||||
andis. r6,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
|
||||
beq L(has_no_vec2)
|
||||
|
||||
cmpdi r10,0
|
||||
@ -646,7 +668,21 @@ L(has_no_vec2):
|
||||
lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
|
||||
lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
|
||||
lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
|
||||
# ifdef _ARCH_PWR6
|
||||
/* Use the extended four-operand version of the mtfsf insn. */
|
||||
mtfsf 0xff,fp0,1,0
|
||||
# else
|
||||
/* Availability of DFP indicates a 64-bit FPSCR. */
|
||||
andi. r6,r8,PPC_FEATURE_HAS_DFP
|
||||
beq 7f
|
||||
/* Use the extended four-operand version of the mtfsf insn. */
|
||||
mtfsf 0xff,fp0,1,0
|
||||
b 8f
|
||||
/* Continue to operate on the FPSCR as if it were 32-bits. */
|
||||
7:
|
||||
mtfsf 0xff,fp0
|
||||
8:
|
||||
#endif /* _ARCH_PWR6 */
|
||||
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
|
||||
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
|
||||
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
|
||||
|
||||
Reference in New Issue
Block a user