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x86: Fix tst-cpu-features-cpuinfo on Ryzen 9 (BZ #27873)
AMD define different flags for IRPB, IBRS, and STIPBP [1], so new x86_64_cpu are added and IBRS_IBPB is only tested for Intel. The SSDB is also defined and implemented different on AMD [2], and also a new AMD_SSDB flag is added. It should map to the cpuinfo 'ssdb' on recent AMD cpus. It fixes tst-cpu-features-cpuinfo and tst-cpu-features-cpuinfo-static on recent AMD cpus. Checked on x86_64-linux-gnu on AMD Ryzen 9 5900X. [1] https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf [2] https://bugzilla.kernel.org/show_bug.cgi?id=199889 Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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@@ -177,6 +177,18 @@ The supported processor features are:
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@item
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@item
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@code{AESKLE} -- AES Key Locker instructions are enabled by OS.
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@code{AESKLE} -- AES Key Locker instructions are enabled by OS.
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@item
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@code{AMD_IBPB} -- Indirect branch predictor barrier (IBPB) for AMD cpus.
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@item
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@code{AMD_IBRS} -- Indirect branch restricted speculation (IBPB) for AMD cpus.
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@item
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@code{AMD_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus.
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@item
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@code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus.
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@item
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@item
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@code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
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@code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
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@@ -278,6 +278,10 @@ enum
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+ cpuid_register_index_ebx * 8 * sizeof (unsigned int)),
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+ cpuid_register_index_ebx * 8 * sizeof (unsigned int)),
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x86_cpu_WBNOINVD = x86_cpu_index_80000008_ebx + 9,
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x86_cpu_WBNOINVD = x86_cpu_index_80000008_ebx + 9,
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x86_cpu_AMD_IBPB = x86_cpu_index_80000008_ebx + 12,
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x86_cpu_AMD_IBRS = x86_cpu_index_80000008_ebx + 14,
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x86_cpu_AMD_STIBP = x86_cpu_index_80000008_ebx + 15,
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x86_cpu_AMD_SSBD = x86_cpu_index_80000008_ebx + 24,
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x86_cpu_index_7_ecx_1_eax
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x86_cpu_index_7_ecx_1_eax
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= (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int)
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= (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int)
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@@ -289,6 +289,10 @@ enum
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/* EBX. */
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/* EBX. */
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#define bit_cpu_WBNOINVD (1u << 9)
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#define bit_cpu_WBNOINVD (1u << 9)
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#define bit_cpu_AMD_IBPB (1u << 12)
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#define bit_cpu_AMD_IBRS (1u << 14)
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#define bit_cpu_AMD_STIBP (1u << 15)
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#define bit_cpu_AMD_SSBD (1u << 24)
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/* CPUID_INDEX_7_ECX_1. */
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/* CPUID_INDEX_7_ECX_1. */
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@@ -519,6 +523,10 @@ enum
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/* EBX. */
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/* EBX. */
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#define index_cpu_WBNOINVD CPUID_INDEX_80000008
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#define index_cpu_WBNOINVD CPUID_INDEX_80000008
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#define index_cpu_AMD_IBPB CPUID_INDEX_80000008
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#define index_cpu_AMD_IBRS CPUID_INDEX_80000008
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#define index_cpu_AMD_STIBP CPUID_INDEX_80000008
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#define index_cpu_AMD_SSBD CPUID_INDEX_80000008
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/* CPUID_INDEX_7_ECX_1. */
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/* CPUID_INDEX_7_ECX_1. */
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@@ -749,6 +757,10 @@ enum
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/* EBX. */
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/* EBX. */
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#define reg_WBNOINVD ebx
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#define reg_WBNOINVD ebx
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#define reg_AMD_IBPB ebx
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#define reg_AMD_IBRS ebx
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#define reg_AMD_STIBP ebx
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#define reg_AMD_SSBD ebx
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/* CPUID_INDEX_7_ECX_1. */
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/* CPUID_INDEX_7_ECX_1. */
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@@ -16,10 +16,11 @@
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License along with the GNU C Library; if not, see
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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<https://www.gnu.org/licenses/>. */
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#include <sys/platform/x86.h>
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#include <cpu-features.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <string.h>
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#include <string.h>
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#include <stdbool.h>
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static char *cpu_flags;
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static char *cpu_flags;
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@@ -99,6 +100,7 @@ static int
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do_test (int argc, char **argv)
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do_test (int argc, char **argv)
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{
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{
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int fails = 0;
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int fails = 0;
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const struct cpu_features *cpu_features = __get_cpu_features ();
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get_cpuinfo ();
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get_cpuinfo ();
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fails += CHECK_PROC (acpi, ACPI);
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fails += CHECK_PROC (acpi, ACPI);
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@@ -159,7 +161,17 @@ do_test (int argc, char **argv)
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fails += CHECK_PROC (hle, HLE);
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fails += CHECK_PROC (hle, HLE);
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fails += CHECK_PROC (ht, HTT);
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fails += CHECK_PROC (ht, HTT);
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fails += CHECK_PROC (hybrid, HYBRID);
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fails += CHECK_PROC (hybrid, HYBRID);
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if (cpu_features->basic.kind == arch_kind_intel)
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{
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fails += CHECK_PROC (ibrs, IBRS_IBPB);
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fails += CHECK_PROC (ibrs, IBRS_IBPB);
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fails += CHECK_PROC (stibp, STIBP);
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}
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else if (cpu_features->basic.kind == arch_kind_amd)
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{
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fails += CHECK_PROC (ibpb, AMD_IBPB);
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fails += CHECK_PROC (ibrs, AMD_IBRS);
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fails += CHECK_PROC (stibp, AMD_STIBP);
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}
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fails += CHECK_PROC (ibt, IBT);
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fails += CHECK_PROC (ibt, IBT);
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fails += CHECK_PROC (invariant_tsc, INVARIANT_TSC);
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fails += CHECK_PROC (invariant_tsc, INVARIANT_TSC);
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fails += CHECK_PROC (invpcid, INVPCID);
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fails += CHECK_PROC (invpcid, INVPCID);
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@@ -221,7 +233,10 @@ do_test (int argc, char **argv)
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fails += CHECK_PROC (smep, SMEP);
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fails += CHECK_PROC (smep, SMEP);
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fails += CHECK_PROC (smx, SMX);
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fails += CHECK_PROC (smx, SMX);
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fails += CHECK_PROC (ss, SS);
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fails += CHECK_PROC (ss, SS);
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if (cpu_features->basic.kind == arch_kind_intel)
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fails += CHECK_PROC (ssbd, SSBD);
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fails += CHECK_PROC (ssbd, SSBD);
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else if (cpu_features->basic.kind == arch_kind_amd)
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fails += CHECK_PROC (ssbd, AMD_SSBD);
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fails += CHECK_PROC (sse, SSE);
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fails += CHECK_PROC (sse, SSE);
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fails += CHECK_PROC (sse2, SSE2);
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fails += CHECK_PROC (sse2, SSE2);
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fails += CHECK_PROC (pni, SSE3);
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fails += CHECK_PROC (pni, SSE3);
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@@ -229,7 +244,6 @@ do_test (int argc, char **argv)
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fails += CHECK_PROC (sse4_2, SSE4_2);
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fails += CHECK_PROC (sse4_2, SSE4_2);
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fails += CHECK_PROC (sse4a, SSE4A);
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fails += CHECK_PROC (sse4a, SSE4A);
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fails += CHECK_PROC (ssse3, SSSE3);
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fails += CHECK_PROC (ssse3, SSSE3);
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fails += CHECK_PROC (stibp, STIBP);
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fails += CHECK_PROC (svm, SVM);
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fails += CHECK_PROC (svm, SVM);
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#ifdef __x86_64__
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#ifdef __x86_64__
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/* NB: SYSCALL_SYSRET is 64-bit only. */
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/* NB: SYSCALL_SYSRET is 64-bit only. */
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