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mirror of https://sourceware.org/git/glibc.git synced 2025-08-08 17:42:12 +03:00

x86: Add support for AVX10 preset and vec size in cpu-features

This commit add support for the new AVX10 cpu features:
https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf

We add checks for:
    - `AVX10`: Check if AVX10 is present.
    - `AVX10_{X,Y,Z}MM`: Check if a given vec class has AVX10 support.

`make check` passes and cpuid output was checked against GNR/DMR on an
emulator.
This commit is contained in:
Noah Goldstein
2023-09-20 15:44:50 -05:00
parent 5f913506f4
commit d90b43a4ed
5 changed files with 83 additions and 3 deletions

View File

@@ -29,7 +29,7 @@
enum
{
CPUID_INDEX_MAX = CPUID_INDEX_14_ECX_0 + 1
CPUID_INDEX_MAX = CPUID_INDEX_24_ECX_0 + 1
};
enum
@@ -319,6 +319,7 @@ enum
#define bit_cpu_AVX_NE_CONVERT (1u << 5)
#define bit_cpu_AMX_COMPLEX (1u << 8)
#define bit_cpu_PREFETCHI (1u << 14)
#define bit_cpu_AVX10 (1u << 19)
#define bit_cpu_APX_F (1u << 21)
/* CPUID_INDEX_19. */
@@ -332,6 +333,13 @@ enum
/* EBX. */
#define bit_cpu_PTWRITE (1u << 4)
/* CPUID_INDEX_24_ECX_0. */
/* EBX. */
#define bit_cpu_AVX10_XMM (1u << 16)
#define bit_cpu_AVX10_YMM (1u << 17)
#define bit_cpu_AVX10_ZMM (1u << 18)
/* CPUID_INDEX_1. */
/* ECX. */
@@ -563,6 +571,7 @@ enum
#define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1
#define index_cpu_AMX_COMPLEX CPUID_INDEX_7_ECX_1
#define index_cpu_PREFETCHI CPUID_INDEX_7_ECX_1
#define index_cpu_AVX10 CPUID_INDEX_7_ECX_1
#define index_cpu_APX_F CPUID_INDEX_7_ECX_1
/* CPUID_INDEX_19. */
@@ -576,6 +585,13 @@ enum
/* EBX. */
#define index_cpu_PTWRITE CPUID_INDEX_14_ECX_0
/* CPUID_INDEX_24_ECX_0. */
/* EBX. */
#define index_cpu_AVX10_XMM CPUID_INDEX_24_ECX_0
#define index_cpu_AVX10_YMM CPUID_INDEX_24_ECX_0
#define index_cpu_AVX10_ZMM CPUID_INDEX_24_ECX_0
/* CPUID_INDEX_1. */
/* ECX. */
@@ -809,6 +825,7 @@ enum
#define reg_AVX_NE_CONVERT edx
#define reg_AMX_COMPLEX edx
#define reg_PREFETCHI edx
#define reg_AVX10 edx
#define reg_APX_F edx
/* CPUID_INDEX_19. */
@@ -822,6 +839,14 @@ enum
/* EBX. */
#define reg_PTWRITE ebx
/* CPUID_INDEX_24_ECX_0. */
/* EBX. */
#define reg_AVX10_XMM ebx
#define reg_AVX10_YMM ebx
#define reg_AVX10_ZMM ebx
/* PREFERRED_FEATURE_INDEX_1. First define the bitindex values
sequentially, then define the bit_arch* and index_arch_* lookup
constants. */