lib/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2025-08-08 17:42:12 +03:00
Code Activity

Restore non-v9 32-bit sparc build.

Browse Source 
* sysdeps/sparc/sparc32/bits/atomic.h: Include sysdep.h to get
	HWCAP_* values only after the memory barriers have been defined.
	(atomic_full_barrier): Define.
	(atomic_read_barrier): Define.
	(atomic_write_barrier): Define.
This commit is contained in:
David S. Miller
2012-04-25 22:24:00 -07:00
parent 6e236b9276
commit cfa1f3e865
2 changed files with 41 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
ChangeLog
View File

@@ -1,3 +1,11 @@
2012-04-25 David S. Miller <davem@davemloft.net>
* sysdeps/sparc/sparc32/bits/atomic.h: Include sysdep.h to get
HWCAP_* values only after the memory barriers have been defined.
(atomic_full_barrier): Define.
(atomic_read_barrier): Define.
(atomic_write_barrier): Define.
2012-04-26 Siddhesh Poyarekar <siddhesh@redhat.com> 2012-04-26 Siddhesh Poyarekar <siddhesh@redhat.com>
* shlib-versions: Add libgcc_s version information. * shlib-versions: Add libgcc_s version information.

34
sysdeps/sparc/sparc32/bits/atomic.h
View File

@@ -21,7 +21,6 @@
#define _BITS_ATOMIC_H 1 #define _BITS_ATOMIC_H 1
#include <stdint.h> #include <stdint.h>
#include <sysdep.h>
typedef int8_t atomic8_t; typedef int8_t atomic8_t;
typedef uint8_t uatomic8_t; typedef uint8_t uatomic8_t;
@@ -231,6 +230,10 @@ volatile unsigned char __sparc32_atomic_locks[64]
abort (); \ abort (); \
__v7_exchange_24_rel (mem, newval); }) __v7_exchange_24_rel (mem, newval); })
# define atomic_full_barrier() __asm ("" ::: "memory")
# define atomic_read_barrier() atomic_full_barrier ()
# define atomic_write_barrier() atomic_full_barrier ()
#else #else
/* In libc.a/libpthread.a etc. we don't know if we'll be run on /* In libc.a/libpthread.a etc. we don't know if we'll be run on
@@ -319,6 +322,35 @@ extern uint64_t _dl_hwcap __attribute__((weak));
__acev_w24ret = __v7_exchange_24_rel (mem, newval); \ __acev_w24ret = __v7_exchange_24_rel (mem, newval); \
__acev_w24ret; }) __acev_w24ret; })
#define atomic_full_barrier() \
do { \
if (__atomic_is_v9) \
/* membar #LoadLoad | #LoadStore | #StoreLoad | #StoreStore */ \
__asm __volatile (".word 0x8143e00f" : : : "memory"); \
else \
__asm __volatile ("" : : : "memory"); \
} while (0)
#define atomic_read_barrier() \
do { \
if (__atomic_is_v9) \
/* membar #LoadLoad | #LoadStore */ \
__asm __volatile (".word 0x8143e005" : : : "memory"); \
else \
__asm __volatile ("" : : : "memory"); \
} while (0)
#define atomic_write_barrier() \
do { \
if (__atomic_is_v9) \
/* membar #StoreLoad | #StoreStore */ \
__asm __volatile (".word 0x8143e00a" : : : "memory"); \
else \
__asm __volatile ("" : : : "memory"); \
} while (0)
#endif #endif
#include <sysdep.h>
#endif /* bits/atomic.h */ #endif /* bits/atomic.h */