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aarch64: Add back non-temporal load/stores from oryon-1's memset
I misunderstood the recommendation from the hardware team about non-temporal load/stores. It is still recommended to use them in memset for large sizes. It was not recommended for their use with device memory and memset is already not valid to be used with device memory. This reverts commit e6590f0c86632c36c9a784cf96075f4be2e920d2. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
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@ -90,6 +90,8 @@ L(set_long):
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cmp count, 256
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ccmp valw, 0, 0, cs
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b.eq L(try_zva)
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cmp count, #32768
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b.hi L(set_long_with_nontemp)
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/* Small-size or non-zero memset does not use DC ZVA. */
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sub count, dstend, dst
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@ -112,6 +114,30 @@ L(set_long):
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stp val, val, [dstend, -16]
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ret
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L(set_long_with_nontemp):
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/* Small-size or non-zero memset does not use DC ZVA. */
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sub count, dstend, dst
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/* Adjust count and bias for loop. By subtracting extra 1 from count,
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it is easy to use tbz instruction to check whether loop tailing
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count is less than 33 bytes, so as to bypass 2 unnecessary stps. */
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sub count, count, 64+16+1
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1: stnp val, val, [dst, 16]
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stnp val, val, [dst, 32]
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stnp val, val, [dst, 48]
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stnp val, val, [dst, 64]
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add dst, dst, #64
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subs count, count, 64
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b.hs 1b
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tbz count, 5, 1f /* Remaining count is less than 33 bytes? */
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stnp val, val, [dst, 16]
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stnp val, val, [dst, 32]
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1: stnp val, val, [dstend, -32]
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stnp val, val, [dstend, -16]
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ret
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L(try_zva):
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/* Write the first and last 64 byte aligned block using stp rather
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than using DC ZVA as it is faster. */
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